{"id":"cpu-out-of-order","level":"compute","name":"Out-of-order CPU pipeline","shortName":"Out-of-order CPU pipeline","role":"Finds ready independent instructions while preserving architectural results.","description":"A CPU often runs code whose next action depends on a branch, pointer or recently loaded value. An out-of-order core searches a window of decoded work for instructions whose inputs are ready. Register renaming separates accidental name reuse from real data dependencies, while a retirement mechanism makes completed work visible in the required order. Prediction can keep the window supplied but wrong predictions waste work. Arm Neoverse V2 provides a public example of rename and issue structures. This organization explains CPU strength in control-heavy services without claiming that every CPU or every workload benefits equally.","specs":[{"label":"Execution window","value":"Finite instruction population","context":"Ready work must fit within implementation queues."},{"label":"Latency versus throughput","value":"Cycles versus instructions/cycle","context":"A long dependent chain can remain slow despite multiple execution units."}],"interfaces":[{"name":"Instruction stream","direction":"in","signal":"Decoded operations, branches and operand names"},{"name":"Architectural state","direction":"out","signal":"Committed registers and ordered memory effects"}],"tradeoff":"Larger windows and prediction structures discover more parallelism but consume area and power; dependent pointer chasing still exposes memory latency.","whyAI":"CPUs prepare batches, tokenize requests, manage runtimes and execute irregular operators that surround dense accelerator kernels.","related":["host-cpu","cpu-vector-matrix","coherence-numa"],"sources":[{"title":"Arm Neoverse V2 Core Technical Reference Manual","url":"https://documentation-service.arm.com/static/633fe1ec4c59b30b517730b8"}],"scale":"Core to multi-socket server; diagrams are logical","kind":"architecture","branch":"Processing architectures","subbranch":"CPU control and locality","mechanism":["Fetch a predicted instruction path so useful work can enter the machine before every branch resolves.","Rename destination registers to avoid false dependencies caused by reusing an architectural register name.","Place operations into queues and issue those whose true operands and execution resources are available.","Wait for a dependent load while allowing unrelated arithmetic or another independent load to proceed.","Retire completed instructions in the required order; squash younger speculative work after a misprediction."],"misconception":"Out-of-order execution changes the internal schedule; it does not authorize arbitrary changes to the program’s observable behavior.","check":{"question":"Which pair offers the best opportunity for overlapping execution?","options":["Two additions using independent inputs","A load followed by a load whose address is the first result","A divide followed by an operation requiring its result"],"answer":0,"explanation":"Independent operands let the issue machinery choose both operations without violating a true data dependency."},"science":[{"title":"Dependency bound","equation":"T ≥ Lcritical / f","explanation":"Lcritical is the dependent path length in cycles and f is clock frequency in cycles/s; T is seconds. Parallel units cannot shorten a strict dependency path.","assumptions":"A simplified bound that omits memory queueing and assumes the identified path remains critical."}],"prerequisites":["host-cpu","register-file"],"learningObjective":"Distinguish true dependence, register naming and speculative scheduling.","workstream":"W07","visualFamily":"architecture-cpu","engineeringExample":"Synthetic trace: a four-cycle multiply and a four-cycle unrelated load may overlap toward four cycles. Making the load address depend on the multiply raises the ideal path toward eight cycles, before cache-miss penalties.","evidenceNotes":"The diagram is a logical pipeline. Queue sizes, prediction accuracy and workload speedups are not inferred from the Arm example.","labId":"library","scope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.","investigationId":"execution","labScope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism."}