{"id":"cowos-s-silicon-interposer","level":"package","name":"CoWoS-S and the silicon interposer route","shortName":"CoWoS-S and the silicon interposer route","role":"Integrates logic and memory over a shared silicon routing structure.","description":"CoWoS-S is a TSMC integration route built around a silicon interposer. Logic dies and separately manufactured HBM stacks meet on that fine-routing structure, which then connects to a package substrate. The interposer is a fabricated component with wiring and vertical connections; it is not the same object as the accelerator die or the organic substrate. Its area, routing, test status and assembly requirements enter the package plan. The process graph therefore converges several supply paths instead of showing HBM emerging from the logic wafer. The cross-section preserves each input’s identity through joining and final package test.","specs":[{"label":"Routing structure","value":"Silicon interposer","context":"Distinct from active logic, HBM stacks and organic substrate."},{"label":"Assembly inputs","value":"Good logic + good memory + interposer + substrate","context":"Counts require compatible product configurations and timing."}],"interfaces":[{"name":"Screened components","direction":"in","signal":"Logic, HBM, interposer and substrate with compatible interfaces"},{"name":"Integrated package","direction":"out","signal":"Fine die-to-memory routing and a board-facing package interface"}],"tradeoff":"A shared dense routing plane supports many connections but requires interposer fabrication and high-value multi-component assembly.","whyAI":"The interposer enables many short parallel connections between compute and HBM; package supply still depends on every converging input.","related":["interposer","hbm-stack","cowos-r-l-routing","hbm-stack-assembly-test"],"sources":[{"title":"TSMC — CoWoS","url":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm"}],"scale":"Multi-die package to selected joint; not dimensionally identical alternatives","kind":"integration","branch":"Packaging / Interposers, bridges and stacking","subbranch":"Alternative integration routes","mechanism":["Fabricate and inspect the silicon interposer and its routing/vertical connection structures.","Manufacture and screen logic dies and memory stacks on their separate upstream routes.","Align and join components to compatible interposer locations using the selected assembly process.","Connect the integrated assembly to the package substrate and complete mechanical/thermal structures.","Test the final package and retain die, memory and interposer genealogy for failures."],"misconception":"HBM is not made after the logic die as a continuation of the same wafer process; its manufacturing path converges at integration.","check":{"question":"If logic dies are plentiful but compatible HBM stacks are scarce, what constrains package output?","options":["The required HBM stack supply can become the binding input","Only the logic wafer-start rate","The silicon atom count of the substrate"],"answer":0,"explanation":"Each finished package consumes a complete compatible set of components."},"science":[{"title":"Convergent assembly ceiling","equation":"N_packages ≤ min(N_logic/l, N_HBM/h, N_interposer, N_substrate, C_assembly)","explanation":"N terms count available good compatible inputs; l and h are logic dies and HBM stacks required per package; C_assembly uses packages over the same interval.","assumptions":"A resource ceiling before new assembly losses, qualification, scheduling and inventory constraints; it is not a yield forecast."}],"prerequisites":["flip-chip-abf-substrate","known-good-die-test"],"learningObjective":"Trace separate logic, memory and interposer paths into a CoWoS-S package.","workstream":"W05","visualFamily":"package-route","engineeringExample":"Synthetic week: 100 logic dies, 320 good HBM stacks and four stacks/package permit at most 80 packages before other constraints, even if 100 interposers and substrates are ready.","evidenceNotes":"TSMC’s public page establishes route identity. Exact process order, materials and customer allocation are not fully public.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}