{"id":"copper-conductor","level":"matter","name":"Copper conductor and barrier","shortName":"Copper wiring","role":"Carries electrical signals and current through much of the chip wiring stack.","description":"Copper wiring connects devices that would otherwise remain isolated islands. In a damascene structure, metal occupies patterned recesses in an insulating material, with barrier and liner layers separating the conductor from its surroundings. Those surrounding films are electrically significant: as a wire becomes narrower, they consume a larger fraction of its available cross section. Resistance therefore does not improve simply because the metal line becomes smaller. Material interfaces, voids, and diffusion control matter alongside copper itself. The atlas shows a cutaway conductor with its enclosure so viewers can distinguish the useful current-carrying area from the supporting films required to make that wire manufacturable and reliable.","specs":[{"label":"Role","value":"Conductor","context":"Used with insulating and diffusion-control films."},{"label":"Resistance trend","value":"R ≈ ρL/A","context":"Bulk geometric intuition; nanoscale effective resistivity also changes."},{"label":"Scaling concern","value":"Barrier/liner fraction","context":"A growing fraction can reduce available copper area."}],"interfaces":[{"name":"Electrical potential difference","direction":"in","signal":"Driving field along the conductor"},{"name":"Connected node","direction":"out","signal":"Current and changing signal voltage"}],"tradeoff":"Thinner barriers leave more copper area. Insufficient barriers can compromise dielectric and interconnect reliability.","whyAI":"Moving operands is part of every AI operation. Wire resistance makes that movement consume time and energy.","related":["dielectric","interconnect","cmp","contact"],"sources":[{"title":"IBM Research — Copper Evolution and Beyond","url":"https://research.ibm.com/blog/beol-cu-interconnects-iedm"}],"scale":"Nanometer-scale local lines through larger global wiring","kind":"conductor","mechanism":["Form an insulating recess that defines where a wire will run.","Separate copper from surrounding material with the required interface films.","Connect the filled conductor to circuit nodes so electrical fields and current can carry signals."],"misconception":"A copper line is not always entirely usable copper cross section; barrier and liner films occupy part of it.","check":{"question":"Why can a narrower copper interconnect have much higher resistance?","options":["The liner becomes a superconducting shell","Its voltage is always zero","Usable copper area shrinks and nanoscale resistivity can increase"],"answer":2,"explanation":"Geometry and material-interface effects both matter; bulk resistivity alone does not fully describe a narrow line."},"branch":"Materials and wiring","subbranch":"Metallization","science":[{"title":"Wire resistance","equation":"R ≈ ρ_eff L / A_Cu","explanation":"A longer line or smaller usable copper cross section increases resistance. The effective resistivity can rise at small dimensions because bulk material behavior no longer captures all scattering and interface effects.","assumptions":"Uniform line approximation; ρ_eff must represent the actual scale and temperature. Barriers, liners, vias, and nonuniform geometry require separate treatment."}],"history":[{"year":1997,"title":"Fully integrated copper wiring demonstrated","significance":"IBM reported integrated CMOS with multiple copper wiring levels, addressing interconnect resistance together with fabrication and reliability. This was a wiring breakthrough, not simply a smaller transistor.","source":{"title":"Edelstein et al. — Full Copper Wiring, IEDM 1997","url":"https://research.ibm.com/publications/full-copper-wiring-in-a-sub-025-mm-cmos-ulsi-technology"}}],"learningObjective":"Trace conductor resistance and barrier tradeoffs through a wiring level.","engineeringExample":"Doubling a line length doubles the distributed resistance in the first-order model; a barrier is required even though it occupies area and adds interface resistance.","evidenceNotes":"The effective resistivity depends on geometry, size effects, temperature and integration details.","visualFamily":"process-wafer","prerequisites":["energy-bands"],"labId":"library","scope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.","investigationId":"switching","labScope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism."}