{"id":"compiler","level":"software","name":"Compiler, intermediate code, and device executable","shortName":"Compiler","role":"Transforms program descriptions into executable instructions and runtime-compatible artifacts.","description":"Compilation bridges the form humans or frameworks express and the instructions hardware executes. In the CUDA toolchain, the compiler driver separates host and device portions, invokes the appropriate compilation stages, and packages device code for use by the host application. Intermediate representations support transformations before final device-specific code is produced, and some paths use runtime compilation. The atlas shows a graph passing through lowering and code-generation stages, with the final launch connected to GPU execution. Optimizations can combine or reorganize operations, but they must preserve the permitted program semantics. A faster compiler path does not change the trained model's intent; it changes how the same required work is mapped to available machinery.","specs":[{"label":"CUDA tool example","value":"NVCC compiler driver","context":"Coordinates host and device compilation stages."},{"label":"Representations","value":"Source → intermediate → target code","context":"Exact stages depend on the toolchain and options."},{"label":"Correctness boundary","value":"Program semantics","context":"Optimizations must respect specified numerical and execution behavior."}],"interfaces":[{"name":"Source or generated program","direction":"in","signal":"Operations and target constraints"},{"name":"Executable artifact","direction":"out","signal":"Device code and host integration"}],"tradeoff":"Specialization can improve execution efficiency. Compilation overhead and target dependence complicate deployment.","whyAI":"Compilers map high-level tensor work onto device instructions. Their choices influence memory traffic, launch overhead, and hardware use.","related":["cuda","kernel","quantization","tensor-core"],"sources":[{"title":"NVIDIA — CUDA Compiler Driver NVCC","url":"https://docs.nvidia.com/cuda/cuda-compiler-driver-nvcc/index.html"}],"scale":"Software transformation graph; no physical size","kind":"compiler","mechanism":["Analyze the program and its target requirements.","Lower and optimize host and device work through the toolchain.","Package or generate executable device code for runtime launch."],"misconception":"A compiler does not discover model weights by itself; training and program translation are different processes.","check":{"question":"What is the compiler’s central job in this layer?","options":["Transform program descriptions into executable forms","Provide emergency electrical power","Replace the training dataset with silicon"],"answer":0,"explanation":"Compilation changes the representation and implementation of a program while preserving its required behavior."},"branch":"Execution software","subbranch":"Compilation","science":[{"title":"Sequential execution-time decomposition","equation":"T ≈ Σ t_launch + Σ t_kernel + Σ t_transfer","explanation":"Compilation and fusion can change the number of launches, intermediate materializations, and execution kernels. This decomposition helps explain a speedup without assuming that fewer kernels always win.","assumptions":"Illustrative sequential baseline without overlap; fused kernels may change register pressure, occupancy, numerical behavior, and actual execution costs."}],"history":[],"learningObjective":"Explain why graph lowering changes movement and launch overhead.","engineeringExample":"A fused operation can remove an intermediate store, but register or shared-memory pressure may reduce occupancy; the tradeoff is workload-specific.","evidenceNotes":"The equation is an execution-time decomposition, not a compiler guarantee.","visualFamily":"software-flow","prerequisites":["kernel"],"labId":"library","scope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.","investigationId":"execution","labScope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism."}