{"id":"coherence-numa","level":"compute","name":"Cache coherence and NUMA placement","shortName":"Cache coherence and NUMA placement","role":"Keeps shared cache lines consistent while preserving awareness of physical memory location.","description":"Multiple CPU cores can cache copies of the same memory line. A coherence protocol tracks copies and coordinates ownership when a core writes. Coherence provides an agreement about values; it does not make every access equally close or eliminate software synchronization. In a NUMA system, memory controllers belong to different locality domains, so an address may be directly attached to one CPU and reached over a link from another. Thread placement and allocation policy determine which path dominates. The Linux kernel documents this distinction and exposes memory policy controls for local, bound and interleaved allocation.","specs":[{"label":"Coherence granularity","value":"Cache line","context":"Independent variables can still share one coherence unit."},{"label":"NUMA latency","value":"Local and remote paths","context":"Nanoseconds depend on machine topology and contention; no universal ratio."}],"interfaces":[{"name":"Core load/store","direction":"in","signal":"Address, ownership request and ordering requirements"},{"name":"Inter-socket fabric","direction":"out","signal":"Remote data or coherence ownership messages"}],"tradeoff":"Interleaving pages can balance memory bandwidth, while placing pages locally can reduce latency; the best choice depends on access sharing and thread migration.","whyAI":"Input pipelines and CPU-managed inference caches can stall accelerators when pages repeatedly cross sockets or writable metadata bounces between cores.","related":["cpu-out-of-order","ddr-memory","memory-hierarchy-route"],"sources":[{"title":"What is NUMA? Linux kernel 6.6 documentation","url":"https://www.kernel.org/doc/html/v6.6/mm/numa.html"}],"scale":"Core to multi-socket server; diagrams are logical","kind":"architecture","branch":"Processing architectures","subbranch":"CPU control and locality","mechanism":["Map an address to its physical NUMA node and identify where the requesting thread is running.","Look for a valid local cache copy before issuing a request toward a memory controller or another cache.","On a write, obtain the protocol’s required ownership and invalidate or update conflicting cached copies.","Place frequently used pages near their workers, or deliberately spread pages when aggregate bandwidth matters more.","Measure remote accesses and cache-line transfers; change allocation and worker affinity together when diagnosing a bottleneck."],"misconception":"Cache coherence is neither a guarantee of low latency nor a substitute for locks, atomics or a language memory model.","check":{"question":"Two cores update different counters in the same cache line. Why might they interfere?","options":["The line’s ownership may move between cores","Different variables can never interfere","NUMA forces all writes to disk"],"answer":0,"explanation":"False sharing occurs because ownership is managed at cache-line granularity even though the variables are logically independent."},"science":[{"title":"Average access path","equation":"Lavg = pLlocal + (1−p)Lremote","explanation":"p is the fraction of accesses using the local path; L values are latency in ns. The average is a first diagnostic, not a tail-latency estimate.","assumptions":"Two paths and independent requests; excludes cache hits, overlap and queueing."}],"prerequisites":["host-cpu","l2-cache"],"learningObjective":"Separate consistency, synchronization and physical locality in shared-memory systems.","workstream":"W07","visualFamily":"architecture-cpu","engineeringExample":"Synthetic two-path example: 75% of requests at 80 ns and 25% at 160 ns gives a 100 ns average. Moving pages changes the fractions; simply adding cores does not shorten either path.","evidenceNotes":"Topology illustrations omit protocol state details. Local-versus-remote numbers are invented for calculation, not measurements of a named CPU.","labId":"library","scope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.","investigationId":"execution","labScope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism."}