{"id":"cmp","level":"matter","name":"Chemical mechanical planarization","shortName":"CMP","role":"Restores controlled surface planarity between fabrication stages.","description":"Building one patterned layer leaves topography that can interfere with the next. Chemical mechanical planarization combines chemical action with a moving pad and abrasive-containing slurry to remove excess material and control surface height. It can expose embedded features and establish a workable foundation for later processing. The process is not simply polishing the finished chip until it shines: material selectivity, remaining film thickness, and uniformity across the wafer matter. The atlas shows a partially planarized wiring surface and the desired plane, making visible why layer stacking requires repeated surface preparation. Measurement and endpoint control keep removal from erasing the structures that the preceding stages worked to create.","specs":[{"label":"Combined mechanism","value":"Chemical + mechanical","context":"A coupled material-removal process."},{"label":"Controlled outputs","value":"Planarity and thickness","context":"Both local patterns and wafer-scale uniformity matter."},{"label":"Integration role","value":"Repeated fabrication step","context":"Used at selected device and wiring stages."}],"interfaces":[{"name":"Uneven patterned surface","direction":"in","signal":"Excess film and topography"},{"name":"Planarized surface","direction":"out","signal":"Foundation for subsequent layers"}],"tradeoff":"Planarity supports the next layer. Excess removal or uneven polishing can damage existing features.","whyAI":"Layered chips require controlled surfaces to remain buildable. CMP helps turn repeated fabrication steps into connected, reliable structures.","related":["silicon-wafer","copper-conductor","lithography","interconnect","interposer"],"sources":[{"title":"Applied Materials — Chemical Mechanical Planarization","url":"https://www.appliedmaterials.com/us/en/semiconductor/products/shape/cmp.html"},{"title":"MIT — Control of Wafer-Scale Nonuniformity in CMP","url":"https://dspace.mit.edu/server/api/core/bitstreams/3190d1a1-d6a9-40d3-83ed-85939659b1f0/content"}],"scale":"Wafer-scale operation controlling nanometer-scale films","kind":"planarization","mechanism":["Identify excess material and topography left by previous fabrication stages.","Use coupled chemical and mechanical action to remove material toward a controlled plane.","Measure the remaining surface and stop before critical underlying structures are damaged."],"misconception":"CMP is not merely cosmetic polishing after chip completion; it supports integration between selected fabrication stages.","check":{"question":"Why is surface planarity important?","options":["It makes the final chip reflective enough to compute","It eliminates the need for lithography","It prepares a controlled foundation for later layers"],"answer":2,"explanation":"Subsequent patterning and material integration depend on controlled surface height and remaining thickness."},"branch":"Fabrication","subbranch":"Planarization","science":[{"title":"Preston removal relation","equation":"RR ≈ k_P P v_rel","explanation":"Removal rate RR is modeled using pressure P, relative sliding speed v_rel, and an empirical coefficient k_P. Chemistry, pad condition, and local pattern geometry influence the coefficient and local behavior.","assumptions":"Empirical approximation over a calibrated regime, not a universal material law or manufacturing recipe; no process settings are prescribed."}],"history":[],"learningObjective":"Explain why planarization needs both removal and local uniformity.","engineeringExample":"A nominally cleared film can still leave slow sites or overpolish fast sites; the CMP lab exposes the two-sided envelope.","evidenceNotes":"The nominal residual is not a spatial mean and is not a bonding-readiness guarantee.","visualFamily":"process-wafer","prerequisites":["silicon-wafer","copper-conductor"],"labId":"engineering","scope":"Compare nominal and local removal-rate extremes at a shared polish time; dishing, erosion and bond readiness are not predicted.","deepLabId":"cmp","investigationId":"manufacturing","labScope":"Compare nominal and local removal-rate extremes at a shared polish time; dishing, erosion and bond readiness are not predicted."}