{"id":"chip-workload-contract","level":"compute","name":"Workload contract and architecture selection","shortName":"Workload contract and architecture selection","role":"Turns desired service behavior into measurable hardware and software requirements.","description":"A custom-chip project begins by defining the work it must perform and the conditions under which success will be measured. A workload contract records operator shapes, numerical quality, latency targets, throughput, state capacity and expected model changes. Architecture exploration then asks how much arithmetic, memory, communication and control are needed together. Existing IP can supply processors, interfaces or other blocks, but its licensing and integration constraints matter. Meta’s MTIA co-design account is one public example of workload-driven development. A chip that excels on one benchmark can still fail the contract if the production graph falls back to a slow unsupported path.","specs":[{"label":"Acceptance unit","value":"Useful workload at fixed quality","context":"For example accepted requests/s under a stated latency target."},{"label":"Requirements horizon","value":"Present mix plus explicit change scenarios","context":"Future operator needs are assumptions, not known measurements."}],"interfaces":[{"name":"Service and model teams","direction":"in","signal":"Representative traces and acceptance criteria"},{"name":"Architecture and software teams","direction":"out","signal":"Resource budgets, supported operations and executable model prototypes"}],"tradeoff":"Specialization improves the frequent path while narrowing flexibility; programmable fallbacks and memory headroom cost area but can extend useful life.","whyAI":"AI models evolve on a different schedule from silicon, so a workload contract must expose assumptions that may fail before a product ships.","related":["inference-custom-silicon","chip-rtl-verification","chip-volume-economics"],"sources":[{"title":"Inside the hardware and co-design of MTIA","url":"https://engineering.fb.com/2024/08/22/ml-applications/meta-mtia-hardware-co-design/"},{"title":"Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration","url":"https://arxiv.org/abs/2203.12268v4"}],"scale":"Design abstractions to manufactured package; not one physical scale","kind":"architecture","branch":"Custom silicon ecosystem","subbranch":"From workload to qualified silicon","mechanism":["Collect production-like traces, including unusual sequence lengths, operator shapes and tail-latency cases.","Define acceptable numerical quality and measurement conditions so the performance target has a stable denominator.","Build resource models for arithmetic, memory traffic, resident state and inter-device communication.","Prototype the compiler and critical kernels against architectural alternatives before fixing the hardware interfaces.","Record unsupported paths and change scenarios, then use these as explicit risks in the architecture decision."],"misconception":"A chip specification is not just a target peak FLOPS number; it is a contract for complete workloads and their operating conditions.","check":{"question":"Which requirement most directly prevents a misleading inference performance target?","options":["A quality threshold and latency condition attached to throughput","The largest possible transistor count","A product name shared with a benchmark winner"],"answer":0,"explanation":"Throughput is only useful when the outputs satisfy the task and arrive under the required service conditions."},"science":[{"title":"Workload-weighted demand","equation":"Dresource = Σk λk qk","explanation":"λk is requests/s for workload class k and qk is bytes or operations per request. Dresource is bytes/s or operations/s.","assumptions":"Linear aggregation before queueing and reuse effects; correlated bursts require an additional capacity margin."}],"prerequisites":["serving","quantization"],"learningObjective":"Translate model behavior and service objectives into a reviewable architecture contract.","workstream":"W08","visualFamily":"design-flow","engineeringExample":"Synthetic mix: 80 requests/s needing 1 GB each and 20 needing 4 GB each creates 160 GB/s of un-reused traffic. Designing from the common 1 GB request alone underestimates the mix by a factor of two.","evidenceNotes":"Workload mix values are synthetic. Public co-design accounts do not reveal a provider’s complete internal traces, IP contracts or acceptance thresholds.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}