{"id":"chip-rtl-verification","level":"compute","name":"RTL and functional verification","shortName":"RTL and functional verification","role":"Checks that a cycle-based design obeys its specification before manufacture.","description":"Register-transfer level code describes how state changes and data moves between registers. Simulation executes that description under selected stimulus; assertions and formal methods test properties under stated assumptions. Coverage asks whether planned situations were exercised, not whether every possible bug has been excluded. An accelerator needs arithmetic checks as well as reset, backpressure, ordering, error and clock-domain behavior. OpenTitan supplies a public example of staged verification planning, reusable test environments and regression evidence. Verification must also cover integrated IP boundaries, because individually correct blocks can disagree about protocols or the meaning of a completed operation.","specs":[{"label":"Verification target","value":"Specification and interface properties","context":"Tests require an expected behavior independent of the implementation."},{"label":"Coverage","value":"Evidence of exercised scenarios","context":"Code or functional coverage is not a mathematical probability of correctness."}],"interfaces":[{"name":"Architecture specification","direction":"in","signal":"Cycle behavior, numerical rules and protocol contracts"},{"name":"Verification evidence","direction":"out","signal":"Assertions, regression results, coverage and unresolved failures"}],"tradeoff":"Exhaustive state exploration grows rapidly; engineers combine abstraction, constrained stimulus, formal properties and targeted tests rather than trusting one technique.","whyAI":"A rare deadlock or wrong accumulator rounding can corrupt long training runs even if the common matrix benchmark appears correct.","related":["flipflop","chip-workload-contract","chip-physical-closure"],"sources":[{"title":"OpenTitan Verification Methodology, Earlgrey 1.0.0","url":"https://opentitan.org/earlgrey_1.0.0/book/doc/contributing/dv/methodology/index.html"}],"scale":"Design abstractions to manufactured package; not one physical scale","kind":"architecture","branch":"Custom silicon ecosystem","subbranch":"From workload to qualified silicon","mechanism":["Write a test plan from externally meaningful requirements, including illegal inputs and recovery behavior.","Construct reference models for arithmetic and protocol state that can detect implementation disagreement.","Drive simulation with directed corner cases and constrained randomized sequences.","Use assertions or formal checks for invariants such as no buffer overwrite before consumption.","Review failures and coverage gaps, then repeat regressions after integration changes and before stage approval."],"misconception":"Passing simulation does not prove all states correct; high coverage does not excuse a missing requirement or an invalid formal assumption.","check":{"question":"What makes a test useful for a hardware handshake?","options":["It checks behavior under backpressure and reset against a protocol rule","It repeats the RTL calculation verbatim","It only counts how often valid is high"],"answer":0,"explanation":"A handshake’s correctness depends on timing and ownership under difficult conditions, not merely exercising signals."},"science":[{"title":"State-space growth","equation":"Nstates = 2^b","explanation":"b is the number of independent state bits and Nstates is a count. Even modest state creates a large space of possible configurations.","assumptions":"A crude upper bound; constraints and abstraction reduce reachable states but must be justified."}],"prerequisites":["flipflop","chip-workload-contract"],"learningObjective":"Explain how simulation, assertions, formal checks and coverage contribute different evidence.","workstream":"W08","visualFamily":"design-flow","engineeringExample":"Synthetic FIFO property: after a valid item is accepted, it must emerge once in order unless reset explicitly cancels it. A test that pauses the consumer reveals bugs hidden by continuous ready signals.","evidenceNotes":"OpenTitan is a methodology example, not an AI accelerator design. Proprietary test coverage and signoff criteria are unknown and are not invented.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}