{"id":"chip-physical-closure","level":"compute","name":"PDKs, synthesis and physical closure","shortName":"PDKs, synthesis and physical closure","role":"Converts logical behavior into a manufacturable layout under electrical constraints.","description":"A process design kit connects circuit design to a fabrication process through device models, layer definitions, design rules and related technology files. Synthesis maps RTL into a cell library; placement and routing assign locations and wires. Extracted resistance and capacitance alter timing and power estimates, so a design that passed logic simulation may need changes after layout. Clock distribution, voltage drop and thermal conditions further constrain operation. OpenROAD provides a public sequence of digital implementation tools, while SKY130 provides an accessible PDK example. Those educational references do not disclose leading-edge foundry recipes or automatically qualify a design for production.","specs":[{"label":"PDK boundary","value":"Models and rules for a specific process","context":"A PDK is not the complete manufacturing recipe."},{"label":"Timing slack","value":"Required arrival − actual arrival, seconds","context":"Positive setup slack alone does not establish hold, power or reliability closure."}],"interfaces":[{"name":"RTL, libraries and PDK","direction":"in","signal":"Logical behavior, cells, parasitic models and layout rules"},{"name":"Verified physical database","direction":"out","signal":"Placed cells, routed nets and signoff evidence"}],"tradeoff":"Upsizing a cell can improve timing while raising capacitance and power; adding buffers or widening wires consumes placement and routing resources.","whyAI":"An accelerator’s dense arithmetic is useful only if clocks, memory interfaces and power delivery meet constraints across the intended operating range.","related":["standard-cell","clock","chip-tapeout-productization"],"sources":[{"title":"SkyWater SKY130 PDK Documentation","url":"https://skywater-pdk.readthedocs.io/en/main/"},{"title":"OpenROAD documentation","url":"https://openroad.readthedocs.io/en/latest/main/README.html"}],"scale":"Design abstractions to manufactured package; not one physical scale","kind":"architecture","branch":"Custom silicon ecosystem","subbranch":"From workload to qualified silicon","mechanism":["Select a process and qualified libraries whose devices, memories and interfaces support the requirements.","Synthesize the RTL and create a floorplan that reserves macro, routing and power-delivery space.","Place cells, distribute clocks and route signals under the technology’s geometry rules.","Extract parasitics and analyze setup, hold, power integrity and other required corners.","Iterate architecture or implementation where constraints conflict, then check physical connectivity and rule compliance with the required signoff flow."],"misconception":"Tapeout-ready layout requires more than a clean RTL simulation; a PDK is neither a chip design nor a universal recipe transferable between nodes.","check":{"question":"A longer routed wire causes a timing failure. Why might pre-layout simulation miss it?","options":["The actual interconnect parasitics were not yet represented accurately","RTL determines physical wire length","All logic gates have zero capacitance"],"answer":0,"explanation":"Physical placement and routing introduce resistance and capacitance that affect signal delay beyond functional logic behavior."},"science":[{"title":"Timing closure model","equation":"Slack = Trequired − (Tcell + Twire)","explanation":"All terms are seconds along a selected timing path; wire delay follows the extracted physical interconnect.","assumptions":"Simplified setup-path model; real analysis includes clock skew, uncertainty, corners and separate hold checks."}],"prerequisites":["standard-cell","interconnect"],"learningObjective":"Describe how process rules and extracted electrical effects constrain a logical design.","workstream":"W08","visualFamily":"design-flow","engineeringExample":"Synthetic path: a 1.0 ns requirement and 0.7 ns cell delay leave 0.3 ns for wires and margin. If extracted wiring adds 0.4 ns, the path misses by 0.1 ns before additional uncertainty.","evidenceNotes":"SKY130’s open documentation warns that the open release is not intended for production use. These examples explain the flow without implying access to commercial signoff decks.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}