{"id":"backside-power-dtco","level":"die","name":"Backside power and design–technology co-optimization","shortName":"Backside power and design–technology co-optimization","role":"Changes physical power routing and evaluates the device, layout and system consequences together.","description":"Power wires and signal wires compete for space and electrical margin. Backside power delivery moves parts of the power network to the opposite side of the wafer through a route that requires additional integration, thinning and connection structures. It can relieve frontside routing constraints, but power still must reach devices reliably and heat still must leave the package. Design–technology co-optimization evaluates cell layout, device structures and routing together; system–technology co-optimization extends that reasoning to partitioning and memory placement. The right comparison asks whether the complete manufacturable system improves at fixed workload requirements, not whether one isolated transistor or wiring metric improves.","specs":[{"label":"Design boundary","value":"Device → cell → die → package","context":"Benefits and costs can appear at different levels."},{"label":"Power metric","value":"Voltage drop and delivery impedance","context":"DC and transient behavior require distinct analyses."}],"interfaces":[{"name":"Workload and physical design","direction":"in","signal":"Current demand, signal routes and technology options"},{"name":"Integrated power architecture","direction":"out","signal":"Device connections, manufacturing route and system constraints"}],"tradeoff":"Relieving frontside congestion can add backside process complexity, alignment demands and new thermal or test considerations.","whyAI":"AI arrays can create substantial current transients and routing demand; integration choices influence sustained operation as well as nominal density.","related":["voltage-regulator","interconnect-rc-materials","temporary-carrier-thinning","gpu-die"],"sources":[{"title":"imec — CMOS scaling","url":"https://www.imec-int.com/en/expertise/cmos-advanced/compute/cmos-scaling"},{"title":"Intel Foundry — Accelerating HPC and AI","url":"https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf"}],"scale":"Contacts to multilayer wires and backside; geometric scale varies","kind":"process","branch":"Fabrication / BEOL and co-design","subbranch":"Interconnect and power integration","mechanism":["Start with the current and routing demands of a defined architecture and workload.","Compare frontside and backside power paths using compatible device and cell assumptions.","Include the thinning, backside connection and alignment operations required by each route.","Analyze DC drop, transient supply noise, signal timing and thermal consequences together.","Recheck yield, test access and package compatibility before claiming a system improvement."],"misconception":"Backside power does not make supply resistance zero or remove the package’s thermal problem.","check":{"question":"What makes a backside-power comparison meaningful?","options":["Only comparing a routing illustration","Assuming every backside process has perfect yield","A common workload and complete device/layout/package assumptions"],"answer":2,"explanation":"Benefits in one physical layer can be offset or amplified elsewhere; a consistent system boundary is necessary."},"science":[{"title":"Supply-path budget","equation":"ΔV ≈ I R + L dI/dt","explanation":"Voltage drop ΔV in V, current I in A, resistance R in Ω, inductance L in H and slew dI/dt in A/s.","assumptions":"First-order lumped path model; distributed power networks and decoupling require frequency-dependent analysis."}],"prerequisites":["interconnect-rc-materials"],"learningObjective":"Evaluate backside power as a coupled design and manufacturing decision.","workstream":"W03","visualFamily":"signal-power","engineeringExample":"Synthetic DC example: a 20 A current through 2 mΩ loses 40 mV before transient effects. Halving that resistance recovers 20 mV, but additional routing or process costs still belong in the comparison.","evidenceNotes":"Intel’s brief includes announced roadmap capabilities. The lesson explains mechanisms and does not equate those announcements with a universal qualified flow.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}