{"id":"adder","level":"logic","name":"Full adder and carry network","shortName":"Adder","role":"Combines binary operands and propagates the carry needed for exact integer addition.","description":"A one-bit full adder accepts two operand bits and a carry input, producing a sum bit and a carry output. Connecting these slices builds wider addition. In a ripple structure, a carry may pass through many consecutive slices before the answer settles. Faster designs compute carry relationships using additional parallel logic, trading more hardware and wiring for reduced depth. The atlas separates sum paths from carry paths so an addition becomes a visible dependency graph rather than a glowing arithmetic box. Signed interpretation, overflow, and finite output width must be specified by the surrounding architecture. The same physical logic can participate in data arithmetic, addresses, counters, and control decisions.","specs":[{"label":"One-bit inputs","value":"A, B, carry-in","context":"Three input bits."},{"label":"Sum equation","value":"S = A XOR B XOR Cin","context":"Exact Boolean relation."},{"label":"Carry equation","value":"Cout = AB + ACin + BCin","context":"Plus denotes Boolean OR."}],"interfaces":[{"name":"Operands and carry","direction":"in","signal":"Binary bit vectors"},{"name":"Sum and carry","direction":"out","signal":"Integer addition result"}],"tradeoff":"Parallel carry logic reduces depth. It adds routing and cell overhead.","whyAI":"Addition combines partial products and accumulations. It also supports the address and control work around matrix operations.","related":["nand","multiplier","mac","flipflop"],"sources":[{"title":"University of Washington CSE 370 — Adders","url":"https://courses.cs.washington.edu/courses/cse370/08au/Lecture%20Slides/Lec14-Adders.pdf"}],"scale":"Microscopic bit slices forming a larger arithmetic block","kind":"adder","mechanism":["Combine each pair of operand bits with the incoming carry condition.","Generate a sum bit and a carry relationship for the next position.","Propagate or compute those carry relationships across the chosen word width."],"misconception":"A carry network is a physical dependency path; writing a plus sign does not make a wide addition instantaneous.","check":{"question":"Why use more elaborate carry logic?","options":["To reduce the depth of carry dependencies","To remove the need to represent input numbers","To make every adder an analog memory"],"answer":0,"explanation":"Parallel carry computation can shorten the waiting path, usually at additional area and routing cost."},"branch":"Arithmetic circuits","subbranch":"Carry propagation","science":[{"title":"Generate and propagate","equation":"G_i = A_i B_i; P_i = A_i ⊕ B_i; C_(i+1) = G_i ∨ (P_i C_i)","explanation":"A bit position either generates a carry or propagates the incoming one. Expanding these relations lets a wider adder compute carry conditions with less serial ripple depth.","assumptions":"Boolean arithmetic with juxtaposition as AND; delay and wiring costs depend on the chosen physical carry network."}],"history":[],"prerequisites":["nand"],"learningObjective":"Trace sum and carry bits through a finite-width binary addition and identify unsigned overflow.","engineeringExample":"Worked four-bit addition: 0111₂ + 0011₂ = 1010₂, or 7 + 3 = 10. For 1111₂ + 0001₂, the stored four-bit sum is 0000₂ and carry-out is 1; discarding that carry changes the represented unsigned result from 16 to 0.","evidenceNotes":"The carry relations follow the linked digital-design lecture. Examples are unsigned four-bit arithmetic; signed overflow is a different condition, and gate delay is outside the truth-table calculation.","labId":"matrix","scope":"Inspect row–column products and accumulated results in a small integer matrix; this does not simulate the individual gate network.","investigationId":"switching","labScope":"Inspect row–column products and accumulated results in a small integer matrix; this does not simulate the individual gate network."}