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  "title": "Wafer maps and good-die yield",
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  "description": "Separates geometrical die count, defects, electrical limits and screened output.",
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      "title": "Wafer maps and good-die yield",
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      "title": "Why can two dies of equal area have different yield?",
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      "title": "Explore in Atlas",
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      "title": "KLA — Chip Manufacturing 101",
      "url": "https://www.kla.com/wp-content/uploads/ChipManufacturing101.pdf"
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    {
      "title": "KLA — Practical Applications of Measurement System Analysis",
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      "title": "Wafer finishing, orientation and geometry",
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  "content": "Fabrication / Control, test and ramp · Atlas v1.3.0\n\n# Wafer maps and good-die yield\n\nSeparates geometrical die count, defects, electrical limits and screened output.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#yield-wafer-defect-model)Feature measurements, wafer maps and time-dependent production\n\nLearning objectiveDistinguish gross die count, model yield and tested usable output.\n\n## The mechanism\n\nA wafer start is not a good die. The wafer geometry first limits how many complete die sites fit, then process defects and electrical specifications determine which sites are usable. Random defects, repeating layout weaknesses and spatial process variation generate different wafer-map patterns. A simple random-defect model is useful for understanding area sensitivity, but it cannot explain every loss mechanism or replace measured yield. Redundancy and binning can also make “good” depend on the product definition. This lesson follows a count from gross sites to tested bins and preserves the population at each stage before linking it to package supply.\n\n1.  Count complete die sites using the actual usable wafer boundary and die/street geometry.\n2.  Distinguish defects likely to kill a die from noncritical inspection findings.\n3.  Compare random-defect expectations with spatial, repeating and parametric loss patterns.\n4.  Apply the defined electrical tests, redundancy rules and product bin criteria.\n5.  Report good output with explicit denominators and retain the wafer map for assembly genealogy.\n\n## Science and assumptions\n\n### Random killer-defect model\n\n$$\nY=\\exp(-D_0A)\n$$\n\nIndependent Poisson fatal-defect survival is the exponential of minus defect density times effective die area.\n\nSymbols and units\n\nY\n\nSurvival probability under the fatal-defect model\n\nfraction\n\nD₀\n\nUniform fatal-defect density\n\ncm⁻²\n\nA\n\nEffective die area\n\ncm²\n\nY is dimensionless die survival probability; D₀ is killer-defect density per cm² and A die area in cm².\n\nAssumptions Independent spatial Poisson defects, each fatal within effective area. Clustering, redundancy, systematic and parametric failures violate this simple model.\n\n## Engineering example\n\nSynthetic example: D₀ = 0.1 cm⁻² and A = 4 cm² give Y ≈ 0.670. A gross count of 100 complete sites then predicts 67 survivors under this model, before separately scoped losses.\n\n## Distinctions and tradeoffs\n\nA Poisson yield curve is not a measured foundry yield or an explanation of every wafer-map pattern.\n\nLarger dies can integrate more function but expose more area to defects and reduce gross dies per wafer.\n\nAccelerator supply depends on good die count and usable bins, not only wafer starts or the number of transistors drawn.\n\n## Specifications and interfaces\n\nYield denominator\n\nGood dies / defined tested or gross population\n\nSpecify whether untested, partial and excluded sites are included.\n\nDefect density\n\nKiller defects per area\n\nA model input, distinct from every optically detected feature.\n\n### Interfaces\n\nWafer geometry and process data Input\n\nComplete sites, defect information and electrical criteria\n\nGood-die population Output\n\nTraceable bins for assembly or further screening\n\n## Check your understanding\n\n### Why can two dies of equal area have different yield?\n\n1.  Testing creates identical transistors\n2.  Layout sensitivity, defect exposure and electrical requirements can differ\n3.  Equal area guarantees equal yield\n\nAnswer and reasoning\n\nLayout sensitivity, defect exposure and electrical requirements can differ\n\nArea is only one input; design and process populations determine which defects and variations are fatal.\n\n## Evidence and scope\n\nNumbers are synthetic. Never multiply an already measured finished-output yield by the same defect loss again.\n\nExplore gross sites and random-defect survival; geometric approximations and defect models do not replace wafer test.\n\n## Sources\n\n-   [KLA — Chip Manufacturing 101](https://www.kla.com/wp-content/uploads/ChipManufacturing101.pdf)\n-   [KLA — Practical Applications of Measurement System Analysis](https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf)\n-   [Advantest — Semiconductor test glossary](https://www.advantest.com/en/investors/ir-library/glossary/)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/yield-wafer-defect-model-58ab8bd67a4d912b.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Wafer finishing, orientation and geometry](https://semiaifoundry.com/learn/atlas/wafer-finishing-geometry/)\n-   [Metrology, inspection and process windows](https://semiaifoundry.com/learn/atlas/fab-metrology-process-window/)\n\n### Related lessons\n\n-   [Wafer and fabrication hierarchy](https://semiaifoundry.com/learn/atlas/silicon-wafer/)\n-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)\n-   [HBM silicon intensity and allocation](https://semiaifoundry.com/learn/atlas/hbm-silicon-intensity/)"
}