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  "title": "Wafer-scale compute and distributed SRAM",
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  "description": "Keeps a very large compute fabric connected across a wafer-scale implementation.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Processing architectures",
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      "title": "Wafer-scale compute and distributed SRAM",
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      "title": "The mechanism",
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      "title": "Distributed storage budget",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "Why is adding every local-link rate misleading for a single external data stream?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#wafer-scale-routing"
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    {
      "title": "Cerebras announces third-generation Wafer Scale Engine",
      "url": "https://www.cerebras.ai/press-release/cerebras-announces-third-generation-wafer-scale-engine"
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      "title": "Six-transistor static memory cell",
      "url": "https://semiaifoundry.com/learn/atlas/sram/"
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    {
      "title": "On-chip interconnect fabric",
      "url": "https://semiaifoundry.com/learn/atlas/on-chip-network/"
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    {
      "title": "Parallelism as a memory and communication budget",
      "url": "https://semiaifoundry.com/learn/atlas/parallelism-communication-budget/"
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  "content": "Processing architectures · Atlas v1.3.0\n\n# Wafer-scale compute and distributed SRAM\n\nKeeps a very large compute fabric connected across a wafer-scale implementation.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#wafer-scale-routing)Network endpoint to wafer; electrical and optical views are conceptual\n\nLearning objectiveSeparate local aggregate capability from external and full-system limits of wafer-scale computing.\n\n## The mechanism\n\nA wafer-scale processor uses a connected area much larger than a conventional reticle-sized logic die. Cerebras WSE-3 provides a public example with many compute elements and distributed on-chip SRAM, integrated into a purpose-built system. The attraction is fine-grained local communication and a large aggregate memory fabric. It also demands mechanisms for defect tolerance, routing around unavailable resources, power delivery and heat removal. Wafer-scale integration still has finite storage, routing capacity and fault-tolerance resources; a larger connected surface does not provide unlimited memory. Large models may still need external state movement or system-level streaming, so aggregate local SRAM bandwidth cannot be substituted for external memory bandwidth.\n\n1.  Partition the model’s operations and state across many local compute-memory regions.\n2.  Use redundant resources and a supported routing map so manufacturing defects do not require every region to be perfect.\n3.  Route intermediate activations through the fabric while keeping reusable state close to its consumer.\n4.  Schedule external transfers for state that cannot remain in distributed local SRAM.\n5.  Close power, cooling and system I/O budgets before treating the connected wafer as deployable capacity.\n\n## Science and assumptions\n\n### Distributed storage budget\n\n$$\nM_{\\mathrm{local}}=\\sum_i M_i,\\qquad T_{\\mathrm{transfer}}\\ge\\frac{Q_{\\mathrm{external}}}{B_{\\mathrm{external}}}\n$$\n\nTotal local capacity sums the storage regions. External transfer time is at least external payload divided by sustainable external bandwidth.\n\nSymbols and units\n\nM\\_local\n\nSummed local storage capacity\n\nbytes\n\nMᵢ\n\nUsable capacity of local storage region i\n\nbytes\n\nT\\_transfer\n\nExternal transfer-time lower bound\n\ns\n\nQ\\_external\n\nPayload bytes crossing the external boundary\n\nbytes\n\nB\\_external\n\nSustainable external payload bandwidth\n\nbytes/s\n\ni\n\nLocal region index\n\ninteger index\n\nMi is local memory in bytes; Qexternal is external bytes moved and Bexternal is sustainable bytes/s.\n\nAssumptions Summed capacity assumes usable placement; fragmentation and replication can lower usable model capacity.\n\n## Engineering example\n\nSynthetic layout: four independent regions each move 1 TB/s locally, but a 0.2 TB/s external port still takes at least 5 ms to supply 1 GB. Summing local links cannot remove that boundary.\n\n## Distinctions and tradeoffs\n\nA wafer-scale chip is not one uniformly accessible giant register, and aggregate on-chip bandwidth is not equivalent to HBM bandwidth at a package boundary.\n\nKeeping communication local can reduce repeated off-chip movement, but the system must handle defects, thermal density and workloads that exceed local state capacity.\n\nModel partitions can exploit a large connected fabric if the compiler balances compute, SRAM and routing rather than merely filling every processing element.\n\n## Specifications and interfaces\n\nPhysical boundary\n\nWafer-scale engine versus complete system\n\nSystem memory, power and cooling are outside the compute-fabric outline.\n\nBandwidth scope\n\nAggregate local versus external\n\nMany simultaneous local links cannot all serve one external transfer.\n\n### Interfaces\n\nDistributed local memory Input\n\nWeights, activations and routed messages\n\nSystem interfaces Output\n\nModel state exchange and completed tensor results\n\n## Check your understanding\n\n### Why is adding every local-link rate misleading for a single external data stream?\n\n1.  The stream must cross its actual interface and topology cuts\n2.  All local links form one external port\n3.  Bandwidth and capacity are the same unit\n\nAnswer and reasoning\n\nThe stream must cross its actual interface and topology cuts\n\nAggregate rates describe parallel local transfers; a particular source-to-destination path is limited by the links and cuts it actually crosses.\n\n## Evidence and scope\n\nWSE-3 announcement facts are vendor-reported. No proprietary defect map, yield, routing algorithm or production price is inferred.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Cerebras announces third-generation Wafer Scale Engine](https://www.cerebras.ai/press-release/cerebras-announces-third-generation-wafer-scale-engine)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/wafer-scale-routing-145b3239e0483607.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Six-transistor static memory cell](https://semiaifoundry.com/learn/atlas/sram/)\n-   [On-chip interconnect fabric](https://semiaifoundry.com/learn/atlas/on-chip-network/)\n\n### Related lessons\n\n-   [Parallelism as a memory and communication budget](https://semiaifoundry.com/learn/atlas/parallelism-communication-budget/)"
}