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  "title": "Through-silicon via",
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  "description": "Provides a vertical electrical connection through silicon between stacked layers.",
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  "revisionDate": "2026-10-07",
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  "topic": "Advanced packaging",
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      "title": "Through-silicon via",
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      "title": "The mechanism",
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      "title": "Via geometry affects electrical resistance",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#through-silicon-via"
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    {
      "title": "SK hynix: Inside 12-layer HBM3 packaging",
      "url": "https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/"
    },
    {
      "title": "Micron HBM3E product brief",
      "url": "https://assets.micron.com/adobe/assets/urn%3Aaaid%3Aaem%3Ab710d8f2-7f66-44c1-a234-456e2b986347/renditions/original/as/hbm3e-product-brief.pdf"
    },
    {
      "title": "MIT: Communication System Design, interconnect and wire scaling",
      "url": "https://ocw.mit.edu/courses/6-973-communication-system-design-spring-2006/44d1cff68d0f994cca25442de3e1ac78_lecture_5.pdf"
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      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
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    {
      "title": "Wafer and fabrication hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/silicon-wafer/"
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    {
      "title": "High-bandwidth memory stack",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack/"
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    {
      "title": "DRAM die and memory banks",
      "url": "https://semiaifoundry.com/learn/atlas/dram-die/"
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  "content": "Advanced packaging · Atlas v1.3.0\n\n# Through-silicon via\n\nProvides a vertical electrical connection through silicon between stacked layers.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#through-silicon-via)Micrometer-scale via features; exact product dimensions undisclosed\n\nLearning objectiveRelate via radius and length to resistance.\n\n## The mechanism\n\nA TSV is a conductive route that passes through the thickness of silicon. In a memory stack, many such routes provide data, control, and power connections between levels and the base. This avoids forcing all communication around the outside edge of each die. The via needs electrical isolation from the surrounding silicon, and its processing must coexist with the circuits and mechanical stresses of thin dies. A TSV is an interconnect through silicon, not a memory bit or a column of stored data. Its conductor is insulated from surrounding silicon, while keep-out and layout constraints separate the connection from nearby circuitry. Connections between surfaces still require bonding structures, so TSVs and microbumps are related but distinct parts.\n\n1.  A via structure is formed through silicon, with insulation separating its conductor from the surrounding material.\n2.  Assembly aligns the via’s surface connections with the adjacent layer or base interface.\n3.  Many vias carry signals and supplies vertically, joining stacked circuits into a connected memory structure.\n\n## Science and assumptions\n\n### Via geometry affects electrical resistance\n\n$$\nR_{\\mathrm{via}}\\approx\\frac{\\rho\\ell}{\\pi r^2}\n$$\n\nVia resistance is approximately resistivity times length divided by its circular conducting area.\n\nSymbols and units\n\nR\\_via\n\nDC via resistance\n\nΩ\n\nρ\n\nEffective conductor resistivity\n\nΩ·m\n\nℓ\n\nConductor length through silicon\n\nm\n\nr\n\nConducting via radius\n\nm\n\nρ is conductor resistivity, ℓ is via length, and r is conductor radius. A shorter or wider conductor lowers its DC resistance. This benefit competes with the silicon area and stress region consumed by the via. Many parallel vertical connections therefore require both electrical design and mechanical/process integration, rather than merely drilling the maximum number of holes.\n\nAssumptions A uniform cylindrical conductor in the ohmic, low-frequency regime. Contact resistance, barrier layers, temperature, skin effects, and size-dependent resistivity are omitted. The equation supplies no proprietary TSV dimensions.\n\n## Engineering example\n\nDoubling via radius quarters the ideal cylindrical resistance at fixed length and resistivity, while keep-out and thermal stress remain.\n\n## Distinctions and tradeoffs\n\nA TSV is a vertical connection, not a column of stored memory bits. The DRAM cells storing those bits are separate circuits beside the interconnect.\n\nDenser vertical connections shorten routes and support more stacked integration, but add process and stress constraints. Thin dies and precise alignment become central assembly challenges.\n\nHBM depends on moving many bits vertically through a compact memory tower. TSVs help turn separate memory dies into a stack with enough connectivity for accelerators.\n\n## Specifications and interfaces\n\nDirection\n\nThrough the die thickness\n\nVertical interconnect rather than surface metal routing.\n\nFunctions\n\nSignals, power, and ground\n\nAssignments depend on the memory-stack design.\n\nStack example\n\n8 or 12 DRAM layers\n\nHBM3E vendor examples; exact via diameter and pitch are not asserted.\n\n### Interfaces\n\nUpper-layer connection Input\n\nElectrical signal or supply\n\nLower-layer connection Output\n\nVertical continuation through silicon\n\nSurface joint Output\n\nConnection through a bump or bonding interface\n\n## Check your understanding\n\n### What does a TSV connect?\n\n1.  Only the server to a distant data center.\n2.  Only photons inside a laser.\n3.  Electrical structures across the thickness of a silicon die.\n\nAnswer and reasoning\n\nElectrical structures across the thickness of a silicon die.\n\nThrough-silicon vias provide vertical electrical routes, which are especially useful when several memory dies are stacked.\n\n## Evidence and scope\n\nTSV geometry and process sequence are route-specific.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [SK hynix: Inside 12-layer HBM3 packaging](https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/)\n-   [Micron HBM3E product brief](https://assets.micron.com/adobe/assets/urn%3Aaaid%3Aaem%3Ab710d8f2-7f66-44c1-a234-456e2b986347/renditions/original/as/hbm3e-product-brief.pdf)\n-   [MIT: Communication System Design, interconnect and wire scaling](https://ocw.mit.edu/courses/6-973-communication-system-design-spring-2006/44d1cff68d0f994cca25442de3e1ac78_lecture_5.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/through-silicon-via-50f0dda1d05a010d.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n-   [Wafer and fabrication hierarchy](https://semiaifoundry.com/learn/atlas/silicon-wafer/)\n\n### Related lessons\n\n-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)\n-   [DRAM die and memory banks](https://semiaifoundry.com/learn/atlas/dram-die/)\n-   [Microbumps and bonding joints](https://semiaifoundry.com/learn/atlas/microbump/)"
}