# Thermal oxidation and the silicon interface

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Revision: 2026-10-07
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Fabrication / Repeated operations · Atlas v1.3.0

# Thermal oxidation and the silicon interface

Converts surface silicon into oxide while moving a buried interface.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#thermal-oxidation-interface)Nanometer films on a wafer; thickness exaggerated

Learning objectiveDistinguish a grown oxide from a deposited film and interpret reaction/transport limits.

## The mechanism

Thermal oxidation grows an oxide by reacting an oxidant with silicon. Unlike simply coating a surface, it consumes part of the substrate and moves the silicon–oxide interface. Oxidant transport through the existing oxide and reaction at the interface can limit growth in different regimes. The oxide can provide insulation or serve a temporary process role, but interface charge and defects affect electrical behavior. Modern gate stacks may use other dielectrics while still depending on carefully prepared interfaces. The animation therefore tracks both the outer film surface and the consumed silicon, then asks which property the next operation actually needs.

1.  Prepare the silicon surface and identify which materials are exposed.
2.  Transport oxidant to the outer oxide surface and through the growing layer.
3.  React at the silicon interface, consuming silicon as oxide forms.
4.  Track the changing growth regime as transport through the film becomes more important.
5.  Measure thickness and relevant electrical/interface properties before subsequent integration.

## Science and assumptions

### Deal–Grove growth model

$$
x^2+Ax=B(t+\tau)
$$

Oxide thickness squared plus the linear length coefficient times thickness equals the parabolic rate coefficient times elapsed time plus equivalent initial-oxide time.

Symbols and units

x

Oxide thickness

μm

A

Deal–Grove linear-rate length parameter

μm

B

Deal–Grove parabolic rate parameter

μm²/s

t

Oxidation time in the selected regime

s

τ

Equivalent time accounting for initial oxide

s

Oxide thickness x and A use length units; B uses length²/time; τ represents an equivalent initial-oxide time.

Assumptions Planar thermal oxidation in an applicable reaction/diffusion regime. Ultrathin films, stress, orientation and modern interfaces can require corrections.

## Engineering example

Synthetic limiting comparison: if growth is diffusion-limited, x² is proportional to time. Doubling oxide thickness then needs approximately four times the oxidation time, assuming unchanged coefficients and negligible initial thickness.

## Distinctions and tradeoffs

Growing oxide does not simply place its full thickness above an unchanged silicon surface.

Longer or hotter processing can grow more oxide while spending thermal budget and changing nearby dopant distributions.

Insulating interfaces help transistors control current with low leakage; their preparation also affects reproducibility across a logic wafer.

## Specifications and interfaces

Transformation

Silicon + oxidant → silicon oxide

Silicon is consumed; deposited oxide has a different growth history.

Measured output

Thickness and interface quality

Electrical quality is not inferred from thickness alone.

### Interfaces

Prepared silicon and oxidant Input

Reactive surface plus controlled thermal exposure

Oxide/interface Output

Insulation or a process mask with a changed underlying surface

## Check your understanding

### Why does a thick oxide often grow more slowly than an initially thin oxide?

1.  Silicon stops containing atoms
2.  Thicker oxide automatically receives less exposure time
3.  Oxidant must traverse a longer existing film

Answer and reasoning

Oxidant must traverse a longer existing film

Transport through the existing oxide can become the limiting resistance even when the external process conditions remain fixed.

## Evidence and scope

The relation is a teaching model. No production oxidation temperature, oxidant mixture or qualified thickness is specified.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [MIT 6.152J — Micro/Nano Processing Technology lecture notes](https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/pages/lecture-notes/)
-   [ASML — How microchips are made](https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made)
-   [Deal and Grove — General Relationship for the Thermal Oxidation of Silicon](https://www.columbia.edu/~leonard/TISSSite/mvbd.html)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/thermal-oxidation-interface-8ebe63f6e1eb5bc8.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Wafer and fabrication hierarchy](https://semiaifoundry.com/learn/atlas/silicon-wafer/)

### Related lessons

-   [Metal gate and high-k dielectric](https://semiaifoundry.com/learn/atlas/gate-stack/)
-   [Implantation, activation and diffusion](https://semiaifoundry.com/learn/atlas/implantation-anneal-diffusion/)
-   [ALD and self-limiting surface reactions](https://semiaifoundry.com/learn/atlas/ald-self-limiting-growth/)