# Six-transistor static memory cell

Canonical: https://semiaifoundry.com/learn/atlas/sram/
Revision: 2026-10-07
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Digital circuits · Atlas v1.3.0

# Six-transistor static memory cell

Retains a local bit using powered feedback and controlled access devices.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#sram)One microscopic bit cell repeated into larger memory arrays

Learning objectiveExplain powered feedback in a 6T SRAM cell and separate cell count from a complete memory macro.

## The mechanism

The canonical six-transistor SRAM cell contains two cross-coupled inverters plus two access transistors. The inverter pair reinforces one of two stable states while power remains applied. A word line enables access to complementary bit lines for reading or writing. Read and write circuitry around the array is essential: a lone cell does not provide a complete addressable memory. The atlas lets viewers inspect one feedback loop and then see it repeated in rows and columns with shared access wiring. This explains both the compactness of an array and the nonzero cost of moving data into and out of it. Static means no periodic refresh requirement, not permanent retention without power.

1.  Use two cross-coupled inverters to reinforce one stable stored state.
2.  Enable access transistors with the selected word line.
3.  Read or change the state through bit lines and the array’s peripheral circuits.

## Science and assumptions

### Feedback equilibria

$$
x=f(y),\qquad y=g(x)
$$

At equilibrium, each storage-node voltage equals its inverter response to the other node voltage.

Symbols and units

x

First storage-node voltage

V

y

Second storage-node voltage

V

f

First inverter static voltage-transfer function

V → V

g

Second inverter static voltage-transfer function

V → V

Two inverter transfer functions constrain both storage-node voltages simultaneously. The useful states are stable equilibria; a central metastable equilibrium separates them.

Assumptions Static two-inverter teaching model with powered feedback; read/write access, noise margins, mismatch, and transient stability need circuit analysis.

## Engineering example

Synthetic 1 KiB payload contains 1,024 × 8 = 8,192 bits. At six transistors per canonical cell, the cell array contains 49,152 transistors before decoders, sense amplifiers, write drivers, redundancy and control are added.

## Distinctions and tradeoffs

Static RAM is volatile: static refers to retention without periodic refresh while powered, not retention after power loss.

Dense cells save area. Read stability, write ability, and leakage constrain sizing and voltage.

On-chip SRAM keeps working data near arithmetic units. Local reuse reduces repeated traffic to more distant memory.

## Specifications and interfaces

Canonical bit cell

6 transistors

Four latch devices plus two access devices.

Retention

While powered

SRAM is volatile.

Array wiring

Word line + bit lines

Decoders and sensing circuits are outside the cell.

### Interfaces

Word line and bit lines Input

Read/write selection and data

Stored bit Output

Local state accessed through array circuitry

## Check your understanding

### What does the canonical 6T cell need to retain data?

1.  A permanent magnetic field
2.  An optical laser refreshing every row
3.  Continued electrical power

Answer and reasoning

Continued electrical power

The stored state is maintained by powered feedback. Removing power loses the guarantee of retained data.

## Evidence and scope

The six-transistor topology follows the linked SRAM lecture. The arithmetic is an ideal payload count, not a physical macro area, transistor total or proof of read/write stability.

Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.

## Sources

-   [MIT 6.152J — CMOS SRAM and Memory](https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/57460d7d1e3ffe8e245f4f2eb3d8f845_lecture18.pdf)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/sram-1dbbb30d55a2b4de.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Complementary CMOS inverter](https://semiaifoundry.com/learn/atlas/inverter/)
-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)

### Related lessons

-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)
-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)
-   [Register file](https://semiaifoundry.com/learn/atlas/register-file/)