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  "title": "Six-transistor static memory cell",
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  "description": "Retains a local bit using powered feedback and controlled access devices.",
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  "revisionDate": "2026-10-07",
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  "topic": "Digital circuits",
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      "title": "Six-transistor static memory cell",
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      "title": "What does the canonical 6T cell need to retain data?",
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      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#sram"
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    {
      "title": "MIT 6.152J — CMOS SRAM and Memory",
      "url": "https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/57460d7d1e3ffe8e245f4f2eb3d8f845_lecture18.pdf"
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      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "Complementary CMOS inverter",
      "url": "https://semiaifoundry.com/learn/atlas/inverter/"
    },
    {
      "title": "Metal–oxide–semiconductor field-effect transistor",
      "url": "https://semiaifoundry.com/learn/atlas/mosfet/"
    },
    {
      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
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    {
      "title": "Standard-cell library and physical design",
      "url": "https://semiaifoundry.com/learn/atlas/standard-cell/"
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  "content": "Digital circuits · Atlas v1.3.0\n\n# Six-transistor static memory cell\n\nRetains a local bit using powered feedback and controlled access devices.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#sram)One microscopic bit cell repeated into larger memory arrays\n\nLearning objectiveExplain powered feedback in a 6T SRAM cell and separate cell count from a complete memory macro.\n\n## The mechanism\n\nThe canonical six-transistor SRAM cell contains two cross-coupled inverters plus two access transistors. The inverter pair reinforces one of two stable states while power remains applied. A word line enables access to complementary bit lines for reading or writing. Read and write circuitry around the array is essential: a lone cell does not provide a complete addressable memory. The atlas lets viewers inspect one feedback loop and then see it repeated in rows and columns with shared access wiring. This explains both the compactness of an array and the nonzero cost of moving data into and out of it. Static means no periodic refresh requirement, not permanent retention without power.\n\n1.  Use two cross-coupled inverters to reinforce one stable stored state.\n2.  Enable access transistors with the selected word line.\n3.  Read or change the state through bit lines and the array’s peripheral circuits.\n\n## Science and assumptions\n\n### Feedback equilibria\n\n$$\nx=f(y),\\qquad y=g(x)\n$$\n\nAt equilibrium, each storage-node voltage equals its inverter response to the other node voltage.\n\nSymbols and units\n\nx\n\nFirst storage-node voltage\n\nV\n\ny\n\nSecond storage-node voltage\n\nV\n\nf\n\nFirst inverter static voltage-transfer function\n\nV → V\n\ng\n\nSecond inverter static voltage-transfer function\n\nV → V\n\nTwo inverter transfer functions constrain both storage-node voltages simultaneously. The useful states are stable equilibria; a central metastable equilibrium separates them.\n\nAssumptions Static two-inverter teaching model with powered feedback; read/write access, noise margins, mismatch, and transient stability need circuit analysis.\n\n## Engineering example\n\nSynthetic 1 KiB payload contains 1,024 × 8 = 8,192 bits. At six transistors per canonical cell, the cell array contains 49,152 transistors before decoders, sense amplifiers, write drivers, redundancy and control are added.\n\n## Distinctions and tradeoffs\n\nStatic RAM is volatile: static refers to retention without periodic refresh while powered, not retention after power loss.\n\nDense cells save area. Read stability, write ability, and leakage constrain sizing and voltage.\n\nOn-chip SRAM keeps working data near arithmetic units. Local reuse reduces repeated traffic to more distant memory.\n\n## Specifications and interfaces\n\nCanonical bit cell\n\n6 transistors\n\nFour latch devices plus two access devices.\n\nRetention\n\nWhile powered\n\nSRAM is volatile.\n\nArray wiring\n\nWord line + bit lines\n\nDecoders and sensing circuits are outside the cell.\n\n### Interfaces\n\nWord line and bit lines Input\n\nRead/write selection and data\n\nStored bit Output\n\nLocal state accessed through array circuitry\n\n## Check your understanding\n\n### What does the canonical 6T cell need to retain data?\n\n1.  A permanent magnetic field\n2.  An optical laser refreshing every row\n3.  Continued electrical power\n\nAnswer and reasoning\n\nContinued electrical power\n\nThe stored state is maintained by powered feedback. Removing power loses the guarantee of retained data.\n\n## Evidence and scope\n\nThe six-transistor topology follows the linked SRAM lecture. The arithmetic is an ideal payload count, not a physical macro area, transistor total or proof of read/write stability.\n\nUse the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.\n\n## Sources\n\n-   [MIT 6.152J — CMOS SRAM and Memory](https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/57460d7d1e3ffe8e245f4f2eb3d8f845_lecture18.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/sram-1dbbb30d55a2b4de.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Complementary CMOS inverter](https://semiaifoundry.com/learn/atlas/inverter/)\n-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)\n\n### Related lessons\n\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)\n-   [Register file](https://semiaifoundry.com/learn/atlas/register-file/)"
}