# Gate sidewall and inner spacers

Canonical: https://semiaifoundry.com/learn/atlas/spacer/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Device physics · Atlas v1.3.0

# Gate sidewall and inner spacers

Separates the gate from neighboring terminal structures and limits parasitic coupling.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#spacer)Nanometer-scale dielectric features; exaggerated in cutaway

Learning objectiveExplain how spacers separate electrostatic and parasitic design goals.

## The mechanism

Spacers are small dielectric structures with large integration consequences. Around the gate, they provide separation from adjacent source/drain regions and contacts. In stacked nanosheet devices, inner spacers occupy regions between sheets near the gate ends, isolating gate material from the source/drain. Their shape influences unwanted gate-to-terminal capacitance and the space available for other device features. The atlas highlights these normally overlooked volumes in a cutaway rather than hiding them behind the gate shell. This is a structural explanation, not a manufacturing recipe: forming uniform spacers requires precise material selectivity and dimensional control. Without these separators, the impressive channel geometry would not translate into the intended electrical device.

1.  Identify the small dielectric volumes between the gate and neighboring terminal structures.
2.  For nanosheets, expose the inner spacers near the ends of the stacked sheets.
3.  Relate their shape to electrical separation, unwanted capacitance, and available access space.

## Science and assumptions

### Parasitic capacitance and transition charge

$$
Q_{\mathrm{par}}=C_{\mathrm{par}}\Delta V,\qquad C_{\mathrm{par}}\propto\frac{\varepsilon_{\mathrm{eff}}A_{\mathrm{eff}}}{d_{\mathrm{eff}}}
$$

Transition charge equals parasitic capacitance times voltage change. A qualitative capacitance model scales with effective permittivity and area, and inversely with separation.

Symbols and units

Q\_par

Charge moved into parasitic capacitance

C

C\_par

Parasitic capacitance

F

ΔV

Voltage change

V

ε\_eff

Effective absolute permittivity

F/m

A\_eff

Effective facing area

m²

d\_eff

Effective separation

m

Each voltage transition charges unintended gate-to-terminal coupling. Spacer geometry changes the effective field paths, connecting a tiny dielectric feature to switching-energy cost.

Assumptions The geometric proportionality is a qualitative capacitor model; fringing fields dominate many real spacer structures and require numerical extraction.

## Engineering example

Increasing effective spacer distance can reduce overlap capacitance but may increase access resistance or complicate source/drain formation.

## Distinctions and tradeoffs

Spacers are functional dielectric structures; deleting them for a cleaner rendering hides essential device anatomy.

More separation can lower capacitance. It also consumes space and can worsen access resistance.

Parasitic capacitance costs energy during switching. Spacer design helps preserve the efficiency promised by advanced transistors.

## Specifications and interfaces

Material class

Dielectric

Electrically separates nearby structures.

Nanosheet feature

Inner spacers

Isolation between gate and source/drain near sheet ends.

Key effect

Parasitic capacitance

Geometry changes unintended electrical coupling.

### Interfaces

Adjacent gate and terminals Input

Electric fields and geometric proximity

Electrical separation Output

Controlled spacing and reduced coupling

## Check your understanding

### What is one role of nanosheet inner spacers?

1.  Transmit optical data through the chip
2.  Replace all source/drain contacts
3.  Separate gate material from source/drain and limit coupling

Answer and reasoning

Separate gate material from source/drain and limit coupling

Inner spacers contribute to the isolation and capacitance control required by the nanosheet geometry.

## Evidence and scope

The parasitic relation is a proportional teaching model, not a process recipe.

Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.

## Sources

-   [imec — Entering the Nanosheet Transistor Era](https://www.imec-int.com/en/articles/entering-nanosheet-transistor-era-0)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/spacer-6a00ad1e827c9557.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Metal gate and high-k dielectric](https://semiaifoundry.com/learn/atlas/gate-stack/)
-   [Source and drain regions](https://semiaifoundry.com/learn/atlas/source-drain/)

### Related lessons

-   [Gate-all-around nanosheet transistor](https://semiaifoundry.com/learn/atlas/gaa/)
-   [Insulators and low-k films](https://semiaifoundry.com/learn/atlas/dielectric/)