# Source and drain regions

Canonical: https://semiaifoundry.com/learn/atlas/source-drain/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Device physics · Atlas v1.3.0

# Source and drain regions

Connects the controlled channel to reservoirs that supply and collect carriers.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#source-drain)Nanometer-scale terminal regions; illustrative device section

Learning objectivePartition on-resistance into channel, access and contact terms.

## The mechanism

Source and drain are engineered semiconductor regions at the ends of the channel. They must connect efficiently to both the channel and metal contacts, making their resistance a substantial part of device design. Doping and material choice affect carrier availability, while epitaxial regions can also introduce useful strain. Advanced p-type device research includes silicon-germanium and germanium-rich approaches, but one research result should not be treated as the recipe for every commercial transistor. The atlas keeps source/drain material distinct from its metal contact. That separation explains why improving the central channel alone may deliver less benefit than expected: current still has to enter and leave through these surrounding structures.

1.  Provide terminal semiconductor regions at the two ends of the controlled channel.
2.  Engineer carrier supply and access through material, doping, and interface choices.
3.  Connect those regions to metal contacts and the surrounding circuit.

## Science and assumptions

### Series resistance budget

$$
R_{\mathrm{on}}\approx R_{\mathrm{channel}}+R_{\mathrm{source}}+R_{\mathrm{drain}}+R_{\mathrm{contacts}}
$$

Total on-state resistance is approximately the sum of channel, source access, drain access and contact contributions.

Symbols and units

R\_on

Total on-state path resistance in the selected regime

Ω

R\_channel

Channel resistance contribution

Ω

R\_source

Source access resistance contribution

Ω

R\_drain

Drain access resistance contribution

Ω

R\_contacts

Combined contact resistance contribution

Ω

A channel improvement helps only the fraction of total resistance that belongs to the channel. Access regions and contacts can therefore limit the benefit of a better central device.

Assumptions Small-signal or resistive on-state bookkeeping over a specified bias regime; actual transistor I–V behavior is nonlinear and the terms can be bias-dependent.

## Engineering example

Reducing only the channel term cannot guarantee lower total $R_{on}$ if contacts and access regions dominate.

## Distinctions and tradeoffs

Source/drain regions and metal contacts are adjacent parts with different roles, not two names for the same object.

Low resistance improves drive current. Material and activation choices must remain compatible with the full device.

Every switching event depends on carrier access. Source/drain engineering prevents that access from limiting useful compute.

## Specifications and interfaces

Electrical role

Carrier reservoirs

Serve the channel through access regions.

Engineering variables

Doping, material, strain

Process- and device-dependent.

Resistance budget

Includes access resistance

Separate from intrinsic channel behavior.

### Interfaces

Metal contact Input

Charge supplied through terminal interface

Channel Output

Carrier injection and collection

## Check your understanding

### Can source/drain access limit a transistor with an excellent channel?

1.  Yes; access and interface resistance remain in the current path
2.  No; channel resistance is the only physical resistance
3.  Only if the chip has no clock

Answer and reasoning

Yes; access and interface resistance remain in the current path

Useful current must enter and leave the channel through the rest of the device. Improving one portion does not erase the others.

## Evidence and scope

The series decomposition is useful for diagnosis; extraction depends on test structures and bias.

Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.

## Sources

-   [imec — Source/Drain Contact Research, IEDM 2017](https://www.imec-int.com/en/articles/imec-achieves-record-low-contact-resistivity-on-ga-doped-ge-source-drain-contacts-for-pmos-transistors)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/source-drain-7722f4d2b2419368.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)
-   [Donor and acceptor doping](https://semiaifoundry.com/learn/atlas/doping/)

### Related lessons

-   [Controllable semiconductor channel](https://semiaifoundry.com/learn/atlas/channel/)
-   [Device contact and interface resistance](https://semiaifoundry.com/learn/atlas/contact/)
-   [Gate sidewall and inner spacers](https://semiaifoundry.com/learn/atlas/spacer/)