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  "id": "atlas-lesson-source-drain-contact-integration",
  "title": "Source/drain, spacers, contacts and MOL",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Connects a gated channel to useful local wiring without bypassing gate control.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
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  "topic": "Fabrication / FEOL and MOL",
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  "version": "1.3.0",
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  "evidenceScope": "No proprietary contact metal, anneal or resistance target is supplied. Product-specific interfaces require measured structures.",
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      "id": "section-1",
      "title": "Source/drain, spacers, contacts and MOL",
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      "title": "The mechanism",
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      "title": "First-order contact scaling",
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      "title": "Engineering example",
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      "title": "Distinctions and tradeoffs",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "Why can a better intrinsic transistor show only a small circuit-speed improvement?",
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      "title": "Sources",
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      "title": "Continue exploring",
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      "title": "Foundations",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#source-drain-contact-integration"
    },
    {
      "title": "Applied Materials — New Ways to Shrink",
      "url": "https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc"
    },
    {
      "title": "imec — Scaling the BEOL: a toolbox of processes and conductors",
      "url": "https://www.imec-int.com/en/imec-magazine/imec-magazine-september-2019/scaling-the-beol-a-toolbox-filled-with-new-processes-boosters-and-conductors"
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    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "Device contact and interface resistance",
      "url": "https://semiaifoundry.com/learn/atlas/contact/"
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    {
      "title": "Gate sidewall and inner spacers",
      "url": "https://semiaifoundry.com/learn/atlas/spacer/"
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    {
      "title": "Implantation, activation and diffusion",
      "url": "https://semiaifoundry.com/learn/atlas/implantation-anneal-diffusion/"
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    {
      "title": "Source and drain regions",
      "url": "https://semiaifoundry.com/learn/atlas/source-drain/"
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    {
      "title": "BEOL layers, damascene and vias",
      "url": "https://semiaifoundry.com/learn/atlas/beol-damascene-vias/"
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  "content": "Fabrication / FEOL and MOL · Atlas v1.3.0\n\n# Source/drain, spacers, contacts and MOL\n\nConnects a gated channel to useful local wiring without bypassing gate control.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#source-drain-contact-integration)Nanometer device cross-sections; reference flow with alternatives\n\nLearning objectiveExplain how source/drain and MOL choices determine the terminal path beyond the channel.\n\n## The mechanism\n\nThe channel cannot drive a circuit until carriers can enter and leave through low-resistance regions and contacts. Source/drain engineering sets doping, geometry and sometimes strain; spacers separate parts of the gate and neighboring structures; contact processing creates an electrical connection to local wiring. The middle of line, or MOL, links these device terminals to the interconnect hierarchy. Smaller contacts can increase resistance and make alignment and interface preparation more difficult. This lesson treats the channel, source/drain and contact as a series path, showing why improving a transistor’s intrinsic channel does not guarantee the same improvement in a finished logic cell.\n\n1.  Form source/drain regions with the required geometry and electrical activity.\n2.  Preserve spacer isolation and the intended relationship between gate and terminal regions.\n3.  Open contact regions and prepare the semiconductor/conductor interface.\n4.  Deposit and pattern contact materials while controlling voids, alignment and nearby dielectric damage.\n5.  Measure contact chains and device behavior to separate channel improvement from external series resistance.\n\n## Science and assumptions\n\n### First-order contact scaling\n\n$$\nR_c\\approx\\frac{\\rho_c}{A},\\qquad R_{\\mathrm{path}}\\approx R_{\\mathrm{channel}}+R_{\\mathrm{access}}+R_{\\mathrm{contacts}}\n$$\n\nContact resistance is approximately specific contact resistivity divided by area. The complete path also includes channel, access-region and combined contact resistance.\n\nSymbols and units\n\nR\\_c\n\nOne contact resistance under uniform injection\n\nΩ\n\nρ\\_c\n\nSpecific contact resistivity\n\nΩ·m²\n\nA\n\nConducting contact area\n\nm²\n\nR\\_path\n\nTotal selected resistive path\n\nΩ\n\nR\\_channel\n\nChannel contribution\n\nΩ\n\nR\\_access\n\nAccess-region contribution\n\nΩ\n\nR\\_contacts\n\nCombined contacts contribution\n\nΩ\n\nR terms use Ω, specific contact resistivity ρ\\_c uses Ω·m² and contact area A uses m².\n\nAssumptions Uniform-current interface approximation; current crowding and transfer length can invalidate simple inverse-area scaling.\n\n## Engineering example\n\nSynthetic series path: 50 Ω channel plus 50 Ω combined access/contact resistance totals 100 Ω. Halving only channel resistance yields 75 Ω, a 25% total reduction rather than 50%.\n\n## Distinctions and tradeoffs\n\nA lower-resistance channel cannot remove resistance introduced by its access regions and contacts.\n\nLarger contacts can reduce resistance while consuming area and tightening nearby routing or spacing constraints.\n\nContact and access resistance can consume voltage and delay budgets before signals reach the accelerator’s larger interconnect network.\n\n## Specifications and interfaces\n\nContact metric\n\nSpecific contact resistivity, Ω·m² or Ω·cm²\n\nArea-normalized interface property; do not confuse it with contact resistance in Ω.\n\nIntegration boundary\n\nFEOL terminal → MOL → BEOL\n\nExact naming boundaries vary by technology.\n\n### Interfaces\n\nDevice terminals Input\n\nDoped semiconductor, spacers and exposed contact surfaces\n\nLocal electrical connections Output\n\nContacts and local wires with controlled resistance and isolation\n\n## Check your understanding\n\n### Why can a better intrinsic transistor show only a small circuit-speed improvement?\n\n1.  Contact resistance is always zero\n2.  The source and drain never connect to wires\n3.  External series resistance and circuit load may dominate\n\nAnswer and reasoning\n\nExternal series resistance and circuit load may dominate\n\nA finished path includes the channel, access regions, interfaces and wires, each with its own contribution.\n\n## Evidence and scope\n\nNo proprietary contact metal, anneal or resistance target is supplied. Product-specific interfaces require measured structures.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Applied Materials — New Ways to Shrink](https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc)\n-   [imec — Scaling the BEOL: a toolbox of processes and conductors](https://www.imec-int.com/en/imec-magazine/imec-magazine-september-2019/scaling-the-beol-a-toolbox-filled-with-new-processes-boosters-and-conductors)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/source-drain-contact-integration-df048eb45cc83e24.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Device contact and interface resistance](https://semiaifoundry.com/learn/atlas/contact/)\n-   [Gate sidewall and inner spacers](https://semiaifoundry.com/learn/atlas/spacer/)\n-   [Implantation, activation and diffusion](https://semiaifoundry.com/learn/atlas/implantation-anneal-diffusion/)\n\n### Related lessons\n\n-   [Source and drain regions](https://semiaifoundry.com/learn/atlas/source-drain/)\n-   [BEOL layers, damascene and vias](https://semiaifoundry.com/learn/atlas/beol-damascene-vias/)"
}