# SoIC and Foveros: vertical integration families

Canonical: https://semiaifoundry.com/learn/atlas/soic-foveros-vertical-routes/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Packaging / Interposers, bridges and stacking · Atlas v1.3.0

# SoIC and Foveros: vertical integration families

Compares named die-stacking routes while preserving their base-die and bonding differences.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#soic-foveros-vertical-routes)Multi-die package to selected joint; not dimensionally identical alternatives

Learning objectiveDistinguish vertical route selection, base-die function and bonding technology.

## The mechanism

Vertical integration places functional dies above other silicon, shortening selected connections and changing the thermal and test problem. TSMC SoIC-X describes dense chip-on-wafer and wafer-on-wafer stacking routes. Intel’s Foveros family spans distinct implementations; its cited brief distinguishes passive-base integration from Foveros Direct 3D with hybrid bonding to an active base. These are technology families, not one universal stack recipe. A vertical assembly can also become an input to a larger package containing lateral links and HBM. The viewer follows the chosen route’s base, upper die and interfaces, and compares thermal access and tested-die selection alongside connection density.

1.  Select a named family variant and specify whether the base contains active circuits or passive routing.
2.  For die-to-wafer, select screened dies and place them onto a receiving wafer; for wafer-to-wafer, match whole wafer arrays.
3.  Prepare and join interfaces using the bonding technology disclosed for that route.
4.  Complete thinning, vertical access and testing operations appropriate to the stack.
5.  Integrate the vertical assembly into its larger package while checking thermal and power paths.

## Science and assumptions

### Unscreened pair yield

$$
Y_{\mathrm{pair}}=\Pr(G_{\mathrm{top}}\cap G_{\mathrm{bottom}})\approx Y_{\mathrm{top}}Y_{\mathrm{bottom}}
$$

Unscreened pair yield is the joint probability that top and bottom dies are good; it factors into the two marginal yields only when their outcomes are independent.

Symbols and units

Y\_pair

Probability an unscreened matched die pair is good before bonding

fraction

G\_top,G\_bottom

Events that the respective matched die is good

events

Y\_top,Y\_bottom

Marginal good-die probabilities for those sites

fractions

Y values are probabilities over matched die sites before bonding.

Assumptions Product form requires independence and no screening. Screened die-to-wafer flows need conditional incoming quality plus new assembly losses.

## Engineering example

Synthetic wafer pair: two independent 90% die-yield wafers have about 81% coincident good sites before bonding losses. Applying 81% to individually screened dies would incorrectly reuse raw wafer losses.

## Distinctions and tradeoffs

All Foveros generations are not identical, and a vertical stack does not automatically imply a particular hybrid-bond pitch.

Denser vertical connections can reduce communication distance while making heat removal, test access and defect propagation more difficult.

Logic/cache or logic/logic partitioning can place useful resources closer, but useful workload benefit depends on the complete memory and thermal design.

## Specifications and interfaces

Route identity

Die-to-wafer vs wafer-to-wafer

Different matching, selection and handling opportunities.

Base function

Passive routing or active circuitry

Must be specified for the selected implementation, not inferred from its position.

### Interfaces

Prepared die or wafer pair Input

Matched interfaces, test status and compatible material stacks

Vertical assembly Output

Short inter-die connections plus new power/thermal/test constraints

## Check your understanding

### What changes when moving from whole-wafer bonding to die-to-wafer placement?

1.  Individual die selection becomes possible, with added placement/handling demands
2.  Every thermal issue disappears
3.  No receiving interface is needed

Answer and reasoning

Individual die selection becomes possible, with added placement/handling demands

The matching unit changes from a full wafer pair to selected dies and their receiving sites.

## Evidence and scope

Branded technologies evolve. The animation must identify the cited variant, and no complete proprietary flow or current product qualification is claimed.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [TSMC — SoIC](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm)
-   [Intel Foundry — Accelerating HPC and AI](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf)
-   [Intel — New Architectures and Technologies Target Expanded Market Opportunities](https://www.intc.com/news-events/press-releases/detail/106/new-intel-architectures-and-technologies-target-expanded)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/soic-foveros-vertical-routes-b82582373422cf13.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)
-   [CoWoS-S and the silicon interposer route](https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/)

### Related lessons

-   [Hybrid bonding: surface state and alignment](https://semiaifoundry.com/learn/atlas/hybrid-bond-surface-alignment/)
-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)
-   [Backside power and design–technology co-optimization](https://semiaifoundry.com/learn/atlas/backside-power-dtco/)