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  "id": "atlas-lesson-soic-foveros-vertical-routes",
  "title": "SoIC and Foveros: vertical integration families",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Compares named die-stacking routes while preserving their base-die and bonding differences.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Packaging / Interposers, bridges and stacking",
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      "id": "section-1",
      "title": "SoIC and Foveros: vertical integration families",
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      "title": "The mechanism",
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      "title": "Science and assumptions",
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      "title": "Unscreened pair yield",
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      "id": "section-5",
      "title": "Engineering example",
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      "title": "Distinctions and tradeoffs",
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      "id": "section-7",
      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "id": "section-10",
      "title": "What changes when moving from whole-wafer bonding to die-to-wafer placement?",
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      "title": "Evidence and scope",
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      "title": "Continue exploring",
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      "end": 5194
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      "title": "Foundations",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#soic-foveros-vertical-routes"
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    {
      "title": "TSMC — SoIC",
      "url": "https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm"
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    {
      "title": "Intel Foundry — Accelerating HPC and AI",
      "url": "https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf"
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    {
      "title": "Intel — New Architectures and Technologies Target Expanded Market Opportunities",
      "url": "https://www.intc.com/news-events/press-releases/detail/106/new-intel-architectures-and-technologies-target-expanded"
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      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "DFT, probe, binning and known-good die",
      "url": "https://semiaifoundry.com/learn/atlas/known-good-die-test/"
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    {
      "title": "CoWoS-S and the silicon interposer route",
      "url": "https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/"
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    {
      "title": "Hybrid bonding: surface state and alignment",
      "url": "https://semiaifoundry.com/learn/atlas/hybrid-bond-surface-alignment/"
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    {
      "title": "Temporary bonding, thinning and singulation",
      "url": "https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/"
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    {
      "title": "Backside power and design–technology co-optimization",
      "url": "https://semiaifoundry.com/learn/atlas/backside-power-dtco/"
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  "content": "Packaging / Interposers, bridges and stacking · Atlas v1.3.0\n\n# SoIC and Foveros: vertical integration families\n\nCompares named die-stacking routes while preserving their base-die and bonding differences.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#soic-foveros-vertical-routes)Multi-die package to selected joint; not dimensionally identical alternatives\n\nLearning objectiveDistinguish vertical route selection, base-die function and bonding technology.\n\n## The mechanism\n\nVertical integration places functional dies above other silicon, shortening selected connections and changing the thermal and test problem. TSMC SoIC-X describes dense chip-on-wafer and wafer-on-wafer stacking routes. Intel’s Foveros family spans distinct implementations; its cited brief distinguishes passive-base integration from Foveros Direct 3D with hybrid bonding to an active base. These are technology families, not one universal stack recipe. A vertical assembly can also become an input to a larger package containing lateral links and HBM. The viewer follows the chosen route’s base, upper die and interfaces, and compares thermal access and tested-die selection alongside connection density.\n\n1.  Select a named family variant and specify whether the base contains active circuits or passive routing.\n2.  For die-to-wafer, select screened dies and place them onto a receiving wafer; for wafer-to-wafer, match whole wafer arrays.\n3.  Prepare and join interfaces using the bonding technology disclosed for that route.\n4.  Complete thinning, vertical access and testing operations appropriate to the stack.\n5.  Integrate the vertical assembly into its larger package while checking thermal and power paths.\n\n## Science and assumptions\n\n### Unscreened pair yield\n\n$$\nY_{\\mathrm{pair}}=\\Pr(G_{\\mathrm{top}}\\cap G_{\\mathrm{bottom}})\\approx Y_{\\mathrm{top}}Y_{\\mathrm{bottom}}\n$$\n\nUnscreened pair yield is the joint probability that top and bottom dies are good; it factors into the two marginal yields only when their outcomes are independent.\n\nSymbols and units\n\nY\\_pair\n\nProbability an unscreened matched die pair is good before bonding\n\nfraction\n\nG\\_top,G\\_bottom\n\nEvents that the respective matched die is good\n\nevents\n\nY\\_top,Y\\_bottom\n\nMarginal good-die probabilities for those sites\n\nfractions\n\nY values are probabilities over matched die sites before bonding.\n\nAssumptions Product form requires independence and no screening. Screened die-to-wafer flows need conditional incoming quality plus new assembly losses.\n\n## Engineering example\n\nSynthetic wafer pair: two independent 90% die-yield wafers have about 81% coincident good sites before bonding losses. Applying 81% to individually screened dies would incorrectly reuse raw wafer losses.\n\n## Distinctions and tradeoffs\n\nAll Foveros generations are not identical, and a vertical stack does not automatically imply a particular hybrid-bond pitch.\n\nDenser vertical connections can reduce communication distance while making heat removal, test access and defect propagation more difficult.\n\nLogic/cache or logic/logic partitioning can place useful resources closer, but useful workload benefit depends on the complete memory and thermal design.\n\n## Specifications and interfaces\n\nRoute identity\n\nDie-to-wafer vs wafer-to-wafer\n\nDifferent matching, selection and handling opportunities.\n\nBase function\n\nPassive routing or active circuitry\n\nMust be specified for the selected implementation, not inferred from its position.\n\n### Interfaces\n\nPrepared die or wafer pair Input\n\nMatched interfaces, test status and compatible material stacks\n\nVertical assembly Output\n\nShort inter-die connections plus new power/thermal/test constraints\n\n## Check your understanding\n\n### What changes when moving from whole-wafer bonding to die-to-wafer placement?\n\n1.  Individual die selection becomes possible, with added placement/handling demands\n2.  Every thermal issue disappears\n3.  No receiving interface is needed\n\nAnswer and reasoning\n\nIndividual die selection becomes possible, with added placement/handling demands\n\nThe matching unit changes from a full wafer pair to selected dies and their receiving sites.\n\n## Evidence and scope\n\nBranded technologies evolve. The animation must identify the cited variant, and no complete proprietary flow or current product qualification is claimed.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [TSMC — SoIC](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm)\n-   [Intel Foundry — Accelerating HPC and AI](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf)\n-   [Intel — New Architectures and Technologies Target Expanded Market Opportunities](https://www.intc.com/news-events/press-releases/detail/106/new-intel-architectures-and-technologies-target-expanded)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/soic-foveros-vertical-routes-b82582373422cf13.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)\n-   [CoWoS-S and the silicon interposer route](https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/)\n\n### Related lessons\n\n-   [Hybrid bonding: surface state and alignment](https://semiaifoundry.com/learn/atlas/hybrid-bond-surface-alignment/)\n-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)\n-   [Backside power and design–technology co-optimization](https://semiaifoundry.com/learn/atlas/backside-power-dtco/)"
}