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  "title": "SIMT execution and divergent branches",
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  "description": "Shares instruction issue across threads while tracking which lanes participate.",
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  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Processing architectures",
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      "title": "SIMT execution and divergent branches",
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      "title": "Masked execution efficiency",
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      "title": "All threads run the same instruction but read widely separated addresses. What is the likely issue?",
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      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#simt-active-lanes"
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    {
      "title": "CUDA C++ Programming Guide",
      "url": "https://docs.nvidia.com/cuda/cuda-c-programming-guide/"
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      "title": "GPU kernel and thread hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/kernel/"
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    {
      "title": "Streaming multiprocessor",
      "url": "https://semiaifoundry.com/learn/atlas/streaming-multiprocessor/"
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  "content": "Processing architectures · Atlas v1.3.0\n\n# SIMT execution and divergent branches\n\nShares instruction issue across threads while tracking which lanes participate.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#simt-active-lanes)GPU execution group to package; schematic topology\n\nLearning objectiveDistinguish divergent control from inefficient address coalescing.\n\n## The mechanism\n\nA GPU kernel describes many threads, but execution resources issue instructions to groups of threads. Threads can have different addresses and control decisions; the machine uses active masks to determine which lanes participate in a particular instruction. When a group takes different branches, the paths may require separate masked execution. Coalescing is a different concern: neighboring addresses can be combined into efficient memory transactions even when the arithmetic is identical. NVIDIA warps and AMD wavefronts instantiate related ideas with generation-specific details. The useful comparison follows the same small operation through these groups, counting both idle lanes and transferred bytes.\n\n1.  Assign logical threads to an execution group under the target architecture’s documented rules.\n2.  Issue a common operation for the lanes whose predicates are active at that point.\n3.  If control flow splits, execute the required paths with masks and reconverge according to the program.\n4.  Translate each participating lane’s address into memory transactions; contiguous addresses usually waste fewer transferred bytes.\n5.  Compare useful outputs, active masks and actual transactions before attributing low performance to insufficient arithmetic units.\n\n## Science and assumptions\n\n### Masked execution efficiency\n\n$$\nu=\\frac{\\sum_i a_i}{\\sum_i s_i}\n$$\n\nMasked-execution efficiency divides all active lane participations by all issued lane slots over the same instructions.\n\nThe introduced $a_{i}$ and $s_{i}$ explicitly name the original $active_{\\mathrm{lanes}}$ and $issued_{\\mathrm{lane,slots}}$ quantities. The denominator must be nonzero.\n\nSymbols and units\n\nu\n\nActive-lane fraction over issued instructions\n\nfraction\n\naᵢ\n\nActive lanes in issued instruction i\n\nlane participations\n\nsᵢ\n\nIssued lane slots available in instruction i\n\nlane slots\n\ni\n\nIssued-instruction index\n\ninteger index\n\nCount lane participation over issued instructions. The resulting fraction measures mask waste and has no time units.\n\nAssumptions Equal-cost instructions in this toy metric; real latency and throughput differ across instructions.\n\n## Engineering example\n\nSynthetic eight-lane group: four lanes require one ten-instruction branch and four require a different ten-instruction branch. If both paths execute under masks, 80 useful lane-instructions occupy 160 issued slots.\n\n## Distinctions and tradeoffs\n\nDivergence and uncoalesced memory access are separate effects; either can occur without the other.\n\nGrouping similar requests can reduce divergence and scattered accesses, but rearranging them costs time and can increase request latency.\n\nIrregular token lengths, sparse experts and gathers can leave SIMD-style resources underused even when a model has a large total operation count.\n\n## Specifications and interfaces\n\nActive-lane fraction\n\nUseful participating lanes / group width\n\nA dimensionless instruction-level metric, distinct from chip utilization.\n\nTransaction efficiency\n\nRequested bytes / transferred bytes\n\nDepends on address alignment, access size and memory behavior.\n\n### Interfaces\n\nKernel threads Input\n\nPer-thread values, predicates and addresses\n\nExecution group Output\n\nMasked instructions and memory transactions\n\n## Check your understanding\n\n### All threads run the same instruction but read widely separated addresses. What is the likely issue?\n\n1.  Memory transaction inefficiency\n2.  Necessarily branch divergence\n3.  Mandatory out-of-order retirement\n\nAnswer and reasoning\n\nMemory transaction inefficiency\n\nUniform control can still generate many memory transactions when the addresses do not fall into shared transaction regions.\n\n## Evidence and scope\n\nThe eight-lane drawing is pedagogical, not a claimed NVIDIA or AMD execution-group width. Cross-vendor scheduling details are intentionally not equated.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [CUDA C++ Programming Guide](https://docs.nvidia.com/cuda/cuda-c-programming-guide/)\n-   [AMD Instinct MI300 Series microarchitecture](https://rocm.docs.amd.com/en/latest/reference/gpu-arch/mi300.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/simt-active-lanes-09a7ed633dfdd537.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [GPU kernel and thread hierarchy](https://semiaifoundry.com/learn/atlas/kernel/)\n-   [Streaming multiprocessor](https://semiaifoundry.com/learn/atlas/streaming-multiprocessor/)\n\n### Related lessons\n\n-   [Occupancy and asynchronous tile pipelines](https://semiaifoundry.com/learn/atlas/gpu-occupancy-pipeline/)"
}