{
  "schemaVersion": 1,
  "id": "atlas-lesson-silicon-wafer",
  "title": "Wafer and fabrication hierarchy",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Provides the shared substrate on which many integrated circuits are fabricated.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/silicon-wafer/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Fabrication",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "Gross-site geometry and yield are teaching estimates; reticle fields, scribe lanes and parametric loss are not hidden.",
  "contentCoverage": "published-lesson",
  "artifactUrl": "https://semiaifoundry.com/ai-atlas/lesson-data/silicon-wafer-d81c84b4d6270976.json",
  "interactiveUrl": "https://semiaifoundry.com/ai-atlas/#silicon-wafer",
  "related": [],
  "supersedes": [],
  "supersededBy": [],
  "contentHash": "088f8000f372f225b9837281ece0d6fc6e5c920388a7d772326b9b447d8019c1",
  "contentLength": 4695,
  "jsonUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-silicon-wafer.json",
  "markdownUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-silicon-wafer.md",
  "sections": [
    {
      "id": "section-1",
      "title": "Wafer and fabrication hierarchy",
      "start": 28,
      "end": 345
    },
    {
      "id": "section-2",
      "title": "The mechanism",
      "start": 345,
      "end": 1330
    },
    {
      "id": "section-3",
      "title": "Science and assumptions",
      "start": 1330,
      "end": 1358
    },
    {
      "id": "section-4",
      "title": "A first defect-yield model",
      "start": 1358,
      "end": 2066
    },
    {
      "id": "section-5",
      "title": "Engineering example",
      "start": 2066,
      "end": 2230
    },
    {
      "id": "section-6",
      "title": "Distinctions and tradeoffs",
      "start": 2230,
      "end": 2588
    },
    {
      "id": "section-7",
      "title": "Specifications and interfaces",
      "start": 2588,
      "end": 2899
    },
    {
      "id": "section-8",
      "title": "Interfaces",
      "start": 2899,
      "end": 3053
    },
    {
      "id": "section-9",
      "title": "Check your understanding",
      "start": 3053,
      "end": 3082
    },
    {
      "id": "section-10",
      "title": "Which order follows physical integration?",
      "start": 3082,
      "end": 3400
    },
    {
      "id": "section-11",
      "title": "Evidence and scope",
      "start": 3400,
      "end": 3662
    },
    {
      "id": "section-12",
      "title": "Sources",
      "start": 3662,
      "end": 4173
    },
    {
      "id": "section-13",
      "title": "Continue exploring",
      "start": 4173,
      "end": 4196
    },
    {
      "id": "section-14",
      "title": "Foundations",
      "start": 4196,
      "end": 4306
    },
    {
      "id": "section-15",
      "title": "Related lessons",
      "start": 4306,
      "end": 4695
    }
  ],
  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#silicon-wafer"
    },
    {
      "title": "Intel — Semiconductors and Intel: An Introduction",
      "url": "https://www.intel.com/content/dam/www/central-libraries/us/en/documents/semiconductors-and-intel-introduction.pdf"
    },
    {
      "title": "Electronic Materials and Fabrication — Productivity and Process Yield",
      "url": "https://staff-old.najah.edu/sites/default/files/Lec29.pdf"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/silicon-wafer-d81c84b4d6270976.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "Diamond-cubic silicon lattice",
      "url": "https://semiaifoundry.com/learn/atlas/crystal-lattice/"
    },
    {
      "title": "Lithography and pattern transfer",
      "url": "https://semiaifoundry.com/learn/atlas/lithography/"
    },
    {
      "title": "Chemical mechanical planarization",
      "url": "https://semiaifoundry.com/learn/atlas/cmp/"
    },
    {
      "title": "Metal–oxide–semiconductor field-effect transistor",
      "url": "https://semiaifoundry.com/learn/atlas/mosfet/"
    },
    {
      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
    }
  ],
  "recordHash": "3e4529ac0fb536c71cf3cdfefb5f3ede217825c12c976f639f69b2e099c84b62",
  "contentFormat": "text/markdown",
  "content": "Fabrication · Atlas v1.3.0\n\n# Wafer and fabrication hierarchy\n\nProvides the shared substrate on which many integrated circuits are fabricated.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#silicon-wafer)300 mm example wafer carrying microscopic structures\n\nLearning objectiveSeparate wafer area, die geometry, starts and good output.\n\n## The mechanism\n\nA wafer is a thin, polished slice of highly purified crystalline silicon. Many die patterns are processed across its surface together before testing and singulation separate usable chips. Device formation near the surface is commonly described as front end of line, or FEOL; local connections bridge devices to the back end of line, or BEOL, wiring stack. These labels describe manufacturing regions, not software front ends and back ends. Repeated patterning, deposition, removal, cleaning, and measurement build the structures layer by layer. The atlas compresses this long chain into a navigable cross section so viewers can connect a macroscopic wafer to the tiny electrical structures it carries.\n\n1.  Begin with a polished crystalline wafer that supports many die locations.\n2.  Build device regions and wiring through repeated patterning and material-processing stages.\n3.  Test the fabricated structures, separate die, and assemble usable die into packages.\n\n## Science and assumptions\n\n### A first defect-yield model\n\n$$\nY\\approx\\exp(-D_0 A_{\\mathrm{die}})\n$$\n\nPoisson die survival is approximately the exponential of minus fatal-defect density times die area.\n\nSymbols and units\n\nY\n\nDie survival probability in the Poisson model\n\nfraction\n\nD₀\n\nUniform fatal-defect density\n\ncm⁻²\n\nA\\_die\n\nEffective die area exposed to those defects\n\ncm²\n\nIf random fatal defects occur at density D₀ per unit area, larger die area increases the chance of encountering one. Yield affects how many functional chips emerge from the same wafer.\n\nAssumptions Illustrative Poisson model with independent uniform fatal defects; real yield uses process-specific models, clustering, repair, and many nonrandom factors.\n\n## Engineering example\n\nA 300 mm wafer with edge exclusion can contain thousands of nominal sites, but the good-die count falls with die area and defect exposure.\n\n## Distinctions and tradeoffs\n\nA wafer, a die, and a package are different objects; one patterned wafer normally contains many die.\n\nLarger useful die area can reduce unit cost. Defects, edge loss, and yield complicate that benefit.\n\nAI accelerators emerge from this manufacturing platform. Wafer yield and die size influence the cost of available compute.\n\n## Specifications and interfaces\n\nExample wafer diameter\n\n300 mm\n\nWidely used advanced-logic manufacturing format; not universal.\n\nThickness\n\nLess than 1 mm\n\nGeneral introductory wafer description, not a procurement specification.\n\nHierarchy\n\nWafer → die → package\n\nTest and assembly intervene between stages.\n\n### Interfaces\n\nPurified crystal Input\n\nMechanically supported semiconductor substrate\n\nFabricated dies Output\n\nPatterned and tested integrated circuits\n\n## Check your understanding\n\n### Which order follows physical integration?\n\n1.  Package → atom → wafer\n2.  Wafer → fabricated die → package\n3.  Metal gate → data center → dopant\n\nAnswer and reasoning\n\nWafer → fabricated die → package\n\nDie are fabricated across a wafer and later separated for assembly. Testing and yield determine which proceed.\n\n## Evidence and scope\n\nGross-site geometry and yield are teaching estimates; reticle fields, scribe lanes and parametric loss are not hidden.\n\nExplore gross sites and random-defect survival; geometric approximations and defect models do not replace wafer test.\n\n## Sources\n\n-   [Intel — Semiconductors and Intel: An Introduction](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/semiconductors-and-intel-introduction.pdf)\n-   [Electronic Materials and Fabrication — Productivity and Process Yield](https://staff-old.najah.edu/sites/default/files/Lec29.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/silicon-wafer-d81c84b4d6270976.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Diamond-cubic silicon lattice](https://semiaifoundry.com/learn/atlas/crystal-lattice/)\n\n### Related lessons\n\n-   [Lithography and pattern transfer](https://semiaifoundry.com/learn/atlas/lithography/)\n-   [Chemical mechanical planarization](https://semiaifoundry.com/learn/atlas/cmp/)\n-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)"
}