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      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#shared-sram"
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      "title": "NVIDIA CUDA: Writing SIMT Kernels",
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      "title": "Six-transistor static memory cell",
      "url": "https://semiaifoundry.com/learn/atlas/sram/"
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  "content": "Memory hierarchy · Atlas v1.3.0\n\n# Shared memory SRAM\n\nLets cooperating threads explicitly stage and reuse a tile near the compute units.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#shared-sram)On-die SRAM banks; logical address map rather than transistor layout\n\nLearning objectiveRelate scratchpad capacity to tile reuse.\n\n## The mechanism\n\nShared memory is a software-managed scratchpad allocated to a thread block. Threads cooperate to load a tile, synchronize when required, and reuse it for several operations before replacing it. Its underlying storage is SRAM, which retains state while powered without the periodic refresh needed by DRAM. Shared memory is banked, so the access pattern matters: requests to different words in the same bank can serialize. Padding or rearranging a tile can remove those conflicts. The capacity is small compared with HBM, but a small tile can be reused many times. Requests that land on the same memory bank can serialize; changing a tile’s layout, for example by padding a matrix transpose, can reduce conflicts without changing its mathematical result.\n\n1.  Cooperating threads or a copy engine bring a reusable tile from device memory into a block’s shared-memory allocation.\n2.  A synchronization point establishes readiness; threads then read the tile repeatedly while computing several outputs.\n3.  The block reuses the scratchpad for another tile, choosing an address layout that avoids conflicting accesses to the same bank.\n\n## Science and assumptions\n\n### Address layout determines bank conflicts\n\n$$\n\\operatorname{bank}(a)=\\left\\lfloor\\frac{a}{4\\,\\mathrm{bytes}}\\right\\rfloor\\bmod32\n$$\n\nDivide the byte address by four bytes, take the floor, then take the remainder modulo 32 to obtain the bank index.\n\nThe explicit four-byte divisor makes the original address-unit convention visible; this mapping is configuration-specific.\n\nSymbols and units\n\na\n\nByte-address offset within the mapped shared-memory address space\n\nbytes\n\nbank(a)\n\nBank index for the addressed word\n\ninteger 0–31\n\n4 bytes\n\nWord width used by this mapping\n\nbytes/word\n\n32\n\nNumber of shared-memory banks\n\ncount\n\na is a byte address for a 32-bit word in the documented shared-memory organization. Adjacent words land in different banks, while addresses separated by 128 bytes return to the same bank. A warp accessing different words in one bank may serialize. Padding a two-dimensional array changes its row stride and can transform a column access from conflicting to distributed.\n\nAssumptions 32 banks and 4-byte word mapping in the referenced CUDA programming model. Wider instructions may be split into transactions; broadcast of the same read address is a special case and is not equivalent to different-word conflicts.\n\n## Engineering example\n\nA tile that exceeds the available scratchpad must be split or reloaded, adding traffic that can erase arithmetic reuse.\n\n## Distinctions and tradeoffs\n\nShared memory and L1 cache are not interchangeable programming concepts. Shared memory is explicitly managed by software; cache retention is automatic.\n\nLarger tiles improve reuse but consume more scratchpad and may reduce active blocks. Bank conflicts can waste this fast storage unless the layout matches the access pattern.\n\nAttention kernels can avoid materializing large intermediate matrices in HBM by combining local tiles with online reductions. The savings come from a better dataflow, not extra model parameters.\n\n## Specifications and interfaces\n\nAddress banks\n\n32 banks\n\nSuccessive 32-bit words map to successive banks in CUDA shared memory.\n\nCapacity per SM\n\nUp to 228 KB\n\nBlackwell compute capability 10.0 shared-memory carveout.\n\nPer-block maximum\n\n227 KB\n\nOne KB reserved by CUDA; dynamic opt-in required above static limits.\n\n### Interfaces\n\nTile staging Input\n\nCoalesced loads or asynchronous copies\n\nTile reuse Output\n\nOperands consumed by cooperating threads\n\nSynchronization Input\n\nBarriers establishing when staged data are ready\n\n## Check your understanding\n\n### Why might adding one padding column to a shared-memory tile improve performance?\n\n1.  It increases HBM capacity.\n2.  It can redirect accesses across different banks and avoid serialization.\n3.  It adds more Tensor Cores to the SM.\n\nAnswer and reasoning\n\nIt can redirect accesses across different banks and avoid serialization.\n\nPadding changes address-to-bank mapping. The arithmetic can stay identical while the memory requests stop competing for the same bank.\n\n## Evidence and scope\n\nThe bank and capacity behavior depends on a specific implementation.\n\nCompare unblocked and tiled matrix traffic for fixed arithmetic; architecture-specific instructions, fusion and attention algorithms are context rather than simulated implementations.\n\n## Sources\n\n-   [NVIDIA CUDA: Writing SIMT Kernels](https://docs.nvidia.com/cuda/archive/13.2.0/cuda-programming-guide/02-basics/writing-cuda-kernels.html)\n-   [NVIDIA CUDA Blackwell Tuning Guide](https://docs.nvidia.com/cuda/blackwell-tuning-guide/index.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/shared-sram-a41c0da718170ae4.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Six-transistor static memory cell](https://semiaifoundry.com/learn/atlas/sram/)\n-   [Register file](https://semiaifoundry.com/learn/atlas/register-file/)\n\n### Related lessons\n\n-   [Streaming multiprocessor](https://semiaifoundry.com/learn/atlas/streaming-multiprocessor/)\n-   [Tensor Core matrix unit](https://semiaifoundry.com/learn/atlas/tensor-core/)\n-   [L1 and texture cache](https://semiaifoundry.com/learn/atlas/l1-cache/)\n-   [Tensor Memory Accelerator](https://semiaifoundry.com/learn/atlas/tensor-memory-accelerator/)"
}