{
  "schemaVersion": 1,
  "id": "atlas-lesson-resist-track-development",
  "title": "Coat, bake, expose and develop",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Creates a temporary resist pattern that guides the following material operation.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/resist-track-development/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Fabrication / Repeated operations",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "No resist formulation, bake setting, developer or exposure dose is specified. Rework eligibility is product and stage dependent.",
  "contentCoverage": "published-lesson",
  "artifactUrl": "https://semiaifoundry.com/ai-atlas/lesson-data/resist-track-development-3b6ecbb447455a88.json",
  "interactiveUrl": "https://semiaifoundry.com/ai-atlas/#resist-track-development",
  "related": [],
  "supersedes": [],
  "supersededBy": [],
  "contentHash": "a1dbd44370df3d2a758e25740efafa4c0c474daf648f66adcacf1fd12797b3c3",
  "contentLength": 5225,
  "jsonUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-resist-track-development.json",
  "markdownUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-resist-track-development.md",
  "sections": [
    {
      "id": "section-1",
      "title": "Coat, bake, expose and develop",
      "start": 50,
      "end": 422
    },
    {
      "id": "section-2",
      "title": "The mechanism",
      "start": 422,
      "end": 1536
    },
    {
      "id": "section-3",
      "title": "Science and assumptions",
      "start": 1536,
      "end": 1564
    },
    {
      "id": "section-4",
      "title": "Pattern-transfer bias",
      "start": 1564,
      "end": 2246
    },
    {
      "id": "section-5",
      "title": "Engineering example",
      "start": 2246,
      "end": 2496
    },
    {
      "id": "section-6",
      "title": "Distinctions and tradeoffs",
      "start": 2496,
      "end": 2871
    },
    {
      "id": "section-7",
      "title": "Specifications and interfaces",
      "start": 2871,
      "end": 3118
    },
    {
      "id": "section-8",
      "title": "Interfaces",
      "start": 3118,
      "end": 3303
    },
    {
      "id": "section-9",
      "title": "Check your understanding",
      "start": 3303,
      "end": 3332
    },
    {
      "id": "section-10",
      "title": "The resist CD is on target but the etched line is too narrow. Which comparison is most useful?",
      "start": 3332,
      "end": 3781
    },
    {
      "id": "section-11",
      "title": "Evidence and scope",
      "start": 3781,
      "end": 4105
    },
    {
      "id": "section-12",
      "title": "Sources",
      "start": 4105,
      "end": 4755
    },
    {
      "id": "section-13",
      "title": "Continue exploring",
      "start": 4755,
      "end": 4778
    },
    {
      "id": "section-14",
      "title": "Foundations",
      "start": 4778,
      "end": 4887
    },
    {
      "id": "section-15",
      "title": "Related lessons",
      "start": 4887,
      "end": 5225
    }
  ],
  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#resist-track-development"
    },
    {
      "title": "ASML — How microchips are made",
      "url": "https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made"
    },
    {
      "title": "MIT 6.152J — Micro/Nano Processing Technology lecture notes",
      "url": "https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/pages/lecture-notes/"
    },
    {
      "title": "KLA — Practical Applications of Measurement System Analysis",
      "url": "https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/resist-track-development-3b6ecbb447455a88.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "Lithography and pattern transfer",
      "url": "https://semiaifoundry.com/learn/atlas/lithography/"
    },
    {
      "title": "Masks, OPC and pattern-aware design",
      "url": "https://semiaifoundry.com/learn/atlas/mask-opc-layout/"
    },
    {
      "title": "DUV, EUV and high-NA imaging",
      "url": "https://semiaifoundry.com/learn/atlas/lithography-resolution-focus/"
    },
    {
      "title": "Plasma and wet etch: selectivity and profile",
      "url": "https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/"
    }
  ],
  "recordHash": "5379ea97e41b5c8bc3d762bdd0f41790a90ad1ff90f38a3d5a104fc5871de64c",
  "contentFormat": "text/markdown",
  "content": "Fabrication / Repeated operations · Atlas v1.3.0\n\n# Coat, bake, expose and develop\n\nCreates a temporary resist pattern that guides the following material operation.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#resist-track-development)Optical field to nanometer pattern; material states distinguished\n\nLearning objectiveIdentify resist-processing states and distinguish their measurements from final geometry.\n\n## The mechanism\n\nA lithographic image first becomes a chemical difference in a resist film. Coating prepares thickness and uniformity; baking changes solvent content or promotes reactions; exposure alters the resist response; development selectively removes material. The remaining pattern is temporary and must survive its next job, often etching a more durable mask. Positive and negative-tone routes do not retain the same exposed regions, so the illustrated route must be named. After-develop geometry is an intermediate result. A clean-looking resist line can still transfer poorly, and its critical dimension is not interchangeable with the final electrical width of a device.\n\n1.  Prepare the surface and coat resist with controlled thickness and uniformity.\n2.  Bake as required by the chosen resist route, preserving a recorded thermal history.\n3.  Expose a patterned image and allow the intended photochemical response.\n4.  Develop the chosen tone and inspect the remaining resist profile.\n5.  Transfer the pattern or rework an eligible wafer according to its actual state and engineering disposition.\n\n## Science and assumptions\n\n### Pattern-transfer bias\n\n$$\nb=\\mathrm{CD}_{\\mathrm{after\\ etch}}-\\mathrm{CD}_{\\mathrm{after\\ develop}}\n$$\n\nTransfer bias is after-etch critical dimension minus after-develop critical dimension at corresponding features.\n\nSymbols and units\n\nb\n\nSigned pattern-transfer bias\n\nnm\n\nCD\\_after etch\n\nCritical dimension after etch at the matched feature definition\n\nnm\n\nCD\\_after develop\n\nCritical dimension after resist development\n\nnm\n\nBoth critical dimensions use the same length unit and corresponding feature definitions; b can be positive or negative.\n\nAssumptions A descriptive difference, not a causal diagnosis. Sidewall shape, sampling and measurement bias must be considered.\n\n## Engineering example\n\nSynthetic measurements: a 24 nm developed resist line corresponds to a 21 nm etched line, giving −3 nm transfer bias. That observation motivates etch/profile and metrology checks; it does not prove a specific etch mechanism.\n\n## Distinctions and tradeoffs\n\nAn after-develop CD is not an after-etch CD, even when both measurements refer to the same nominal line.\n\nA resist must balance sensitivity, resolution, roughness and process robustness while meeting etch-mask requirements.\n\nDense logic and memory structures require repeatable temporary patterns before durable device geometry can be formed.\n\n## Specifications and interfaces\n\nMeasurement stage\n\nAfter develop\n\nResist geometry before subsequent etch or removal.\n\nResponse variables\n\nCD, profile, roughness and defects\n\nCD is critical dimension; report length units and feature definition.\n\n### Interfaces\n\nWafer, resist and exposure Input\n\nSurface preparation, coated film and patterned energy\n\nDeveloped resist Output\n\nTemporary masking geometry and residual surface state\n\n## Check your understanding\n\n### The resist CD is on target but the etched line is too narrow. Which comparison is most useful?\n\n1.  A wafer-average final yield alone\n2.  Only the advertised scanner resolution\n3.  Matched after-develop and after-etch geometry on the same feature class\n\nAnswer and reasoning\n\nMatched after-develop and after-etch geometry on the same feature class\n\nMatching the stages reveals whether the discrepancy appears during imaging or during transfer.\n\n## Evidence and scope\n\nNo resist formulation, bake setting, developer or exposure dose is specified. Rework eligibility is product and stage dependent.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [ASML — How microchips are made](https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made)\n-   [MIT 6.152J — Micro/Nano Processing Technology lecture notes](https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/pages/lecture-notes/)\n-   [KLA — Practical Applications of Measurement System Analysis](https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/resist-track-development-3b6ecbb447455a88.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Lithography and pattern transfer](https://semiaifoundry.com/learn/atlas/lithography/)\n\n### Related lessons\n\n-   [Masks, OPC and pattern-aware design](https://semiaifoundry.com/learn/atlas/mask-opc-layout/)\n-   [DUV, EUV and high-NA imaging](https://semiaifoundry.com/learn/atlas/lithography-resolution-focus/)\n-   [Plasma and wet etch: selectivity and profile](https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/)"
}