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  "topic": "Memory hierarchy",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#register-file"
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    {
      "title": "NVIDIA CUDA Blackwell Tuning Guide",
      "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/index.html"
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    {
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      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "Edge-triggered D flip-flop",
      "url": "https://semiaifoundry.com/learn/atlas/flipflop/"
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    {
      "title": "Six-transistor static memory cell",
      "url": "https://semiaifoundry.com/learn/atlas/sram/"
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      "title": "Streaming multiprocessor",
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      "url": "https://semiaifoundry.com/learn/atlas/l1-cache/"
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  "content": "Memory hierarchy · Atlas v1.3.0\n\n# Register file\n\nKeeps each active thread’s immediate values close to the arithmetic pipelines.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#register-file)On-die storage banks; physical bank dimensions are schematic\n\nLearning objectiveExplain why registers can limit occupancy.\n\n## The mechanism\n\nRegisters hold the addresses, counters, partial results, and scalar operands that threads need immediately. The compiler assigns program values to a finite physical pool. A value in a register does not need a fresh trip to off-chip memory for every instruction. If a kernel asks for too many registers, fewer blocks may fit at once; some values may also spill into local memory, which is backed by device memory and cached. Registers are private to a thread in the programming model, although explicit warp shuffle instructions can exchange values between participating threads. Local register reuse keeps operands near arithmetic lanes; a spill adds memory traffic and can lengthen the path to the same result.\n\n1.  The compiler maps frequently used thread values to registers, subject to the available register pool and allocation rules.\n2.  Execution pipelines repeatedly read and update those nearby values without fetching them anew from HBM.\n3.  If register demands exceed a useful allocation, parallel residency can fall or values can spill to device-backed local memory.\n\n## Science and assumptions\n\n### Register allocation limits resident work\n\n$$\nB_{\\mathrm{resident}}\\le\\left\\lfloor\\frac{R_{\\mathrm{SM}}}{r_{\\mathrm{thread}}T_{\\mathrm{block}}}\\right\\rfloor\n$$\n\nResident blocks cannot exceed the floor of available registers divided by registers per thread times threads per block.\n\nSymbols and units\n\nB\\_resident\n\nBlocks permitted by the register-only budget\n\nblocks/SM\n\nR\\_SM\n\nAvailable 32-bit register slots per SM\n\nregisters/SM\n\nr\\_thread\n\nRegister slots requested by one thread\n\nregisters/thread\n\nT\\_block\n\nThreads in one block\n\nthreads/block\n\nRSM is the number of available 32-bit registers per SM, rthread is registers requested per thread, and Tblock is threads per block. Their product estimates the register footprint of one block. Doubling the per-thread requirement can reduce the number of blocks that fit, even though it may save loads by retaining more intermediate results.\n\nAssumptions A register-only upper bound, assuming uniform allocation. Hardware allocation granularity, reserved resources, warp/block limits, and shared-memory use can lower residency further. It is not a complete CUDA occupancy calculator.\n\n## Engineering example\n\nIf each thread consumes more registers, floor($R_{SM}$/($r_{\\mathrm{thread}}$ $T_{\\mathrm{block}}$)) decreases even if arithmetic units remain available.\n\n## Distinctions and tradeoffs\n\nCUDA local memory does not mean physically nearest to a thread. Register spills to local memory are backed by device memory and may be cached.\n\nKeeping more intermediates in registers can reduce traffic, but large allocations limit parallel residency. Kernel fusion therefore needs a balance between reuse and register pressure.\n\nMatrix kernels, normalization, and attention all reuse small values many times. Register allocation can change their speed even when the mathematical model remains identical.\n\n## Specifications and interfaces\n\nPool per SM\n\n64K × 32-bit registers\n\nBlackwell architectural register-file count.\n\nPer-thread limit\n\n255 registers\n\nArchitectural maximum; allocation granularity and occupancy also matter.\n\nWarp exchange\n\nShuffle instructions\n\nExplicit register-value exchange among participating warp threads.\n\n### Interfaces\n\nLoad or computation Input\n\nThread-local values\n\nExecution operands Output\n\nAddresses and arithmetic inputs\n\nSpill path Output\n\nValues moved to device-backed local memory\n\n## Check your understanding\n\n### What can happen when each thread uses many more registers?\n\n1.  The GPU gains more physical register capacity automatically.\n2.  The model becomes permanently stored on the die.\n3.  Fewer blocks fit concurrently, or some values spill.\n\nAnswer and reasoning\n\nFewer blocks fit concurrently, or some values spill.\n\nRegisters are a finite resource shared among resident work. More per-thread state can trade local reuse for lower concurrency or extra memory traffic.\n\n## Evidence and scope\n\nThe model ignores allocation granularity, spilling and architecture-specific limits.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [NVIDIA CUDA Blackwell Tuning Guide](https://docs.nvidia.com/cuda/blackwell-tuning-guide/index.html)\n-   [NVIDIA: Register Cache for Warp-Centric CUDA Programs](https://developer.nvidia.com/blog/register-cache-warp-cuda/)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/register-file-a316c3c8ecd82c48.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Edge-triggered D flip-flop](https://semiaifoundry.com/learn/atlas/flipflop/)\n-   [Six-transistor static memory cell](https://semiaifoundry.com/learn/atlas/sram/)\n\n### Related lessons\n\n-   [Streaming multiprocessor](https://semiaifoundry.com/learn/atlas/streaming-multiprocessor/)\n-   [Tensor Core matrix unit](https://semiaifoundry.com/learn/atlas/tensor-core/)\n-   [L1 and texture cache](https://semiaifoundry.com/learn/atlas/l1-cache/)\n-   [GPU kernel and thread hierarchy](https://semiaifoundry.com/learn/atlas/kernel/)"
}