# Redistribution layers and fan-out packaging

Canonical: https://semiaifoundry.com/learn/atlas/rdl-fanout-integration/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Packaging / Materials and assembly · Atlas v1.3.0

# Redistribution layers and fan-out packaging

Routes die connections through added layers that can extend beyond the die footprint.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#rdl-fanout-integration)Die pads to package and board; routing pitch schematic

Learning objectiveExplain RDL function and why fan-out route order affects alignment.

## The mechanism

A redistribution layer adds conductive routing over a prepared surface to move connection locations. Fan-out packaging can place dies in a larger reconstructed or molded area and build routing that extends beyond the original die edge. This provides more room for external connections or multiple components, but the reconstructed geometry brings alignment, warpage and material challenges. Chip-first and chip-last flows do not use the same operation order, so the reference sequence names its route. RDL is also a building block in several advanced integration families; seeing it in a package does not establish that every such package has an identical interposer or assembly process.

1.  Choose and label a chip-first or chip-last reference route before animating its sequence.
2.  Create a stable reconstruction or carrier surface with recorded die positions.
3.  Build dielectric, openings and conductive redistribution using the route’s compatible processing steps.
4.  Account for die shift, surface distortion and alignment while connecting original pads.
5.  Release temporary support where required, complete joints and inspect electrical and mechanical integrity.

## Science and assumptions

### Registration budget

$$
e_{\mathrm{total}}^2\approx e_{\mathrm{place}}^2+e_{\mathrm{pattern}}^2+e_{\mathrm{distortion}}^2
$$

For independent zero-mean alignment contributions, the combined squared error is approximately the sum of their squared contributions.

Symbols and units

e\_total

Combined standard-deviation-like alignment contribution

μm

e\_place

Placement contribution

μm

e\_pattern

Patterning contribution

μm

e\_distortion

Residual distortion contribution

μm

Each e is a standard-deviation-like alignment contribution in the same length unit.

Assumptions Root-sum-square model only for independent zero-mean contributions. Systematic offsets must be corrected or budgeted explicitly.

## Engineering example

Synthetic independent alignment terms of 2, 1 and 2 μm combine to 3 μm RMS. If the 2 μm placement term is systematic, averaging more measurements does not erase its physical offset.

## Distinctions and tradeoffs

Fan-out does not simply mean a physically larger silicon die; added routing can occupy a different surrounding material.

Extending routing area can reduce pad-density pressure but increases reconstructed-surface alignment and thermomechanical demands.

Package-level routing can combine useful dies and interfaces when a single monolithic die or direct substrate escape is impractical.

## Specifications and interfaces

Geometry

Die footprint vs reconstructed package area

Fan-out refers to routing beyond the original die boundary.

RDL function

Redistributed signal and power connections

RDL can appear in several process and package families.

### Interfaces

Dies and temporary/reconstructed surface Input

Placement map and compatible exposed connection sites

Redistributed interface Output

New routing and external pad arrangement

## Check your understanding

### Why can die placement error matter before RDL patterning?

1.  A molded surface automatically corrects all coordinates
2.  Redistribution carries no current
3.  The later routing must land on the actual die-pad positions

Answer and reasoning

The later routing must land on the actual die-pad positions

Geometric mismatch between planned routes and real pads can cause opens or shorts even if each die itself is good.

## Evidence and scope

The lesson shows a generic reconstruction sequence, not a vendor’s complete fan-out recipe or qualified alignment budget.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [SK hynix — Small Size, Big Impact](https://news.skhynix.com/en/small-size-big-impact/)
-   [TSMC — CoWoS](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm)
-   [Amkor — Flip Chip Packaging](https://amkor.com/technology/flip-chip/)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/rdl-fanout-integration-495fe537b597d1ea.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Flip-chip assembly and organic substrates](https://semiaifoundry.com/learn/atlas/flip-chip-abf-substrate/)
-   [Wafer handling, carriers and genealogy](https://semiaifoundry.com/learn/atlas/wafer-handling-genealogy/)

### Related lessons

-   [CoWoS-R and CoWoS-L: RDL and local silicon](https://semiaifoundry.com/learn/atlas/cowos-r-l-routing/)
-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)