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  "id": "atlas-lesson-pcie-interface",
  "title": "PCI Express interconnect",
  "category": "learning",
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  "description": "Connects host processors, accelerators, storage, and network adapters through standardized serial links.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Connectivity",
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    {
      "id": "section-1",
      "title": "PCI Express interconnect",
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      "id": "section-2",
      "title": "The mechanism",
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      "title": "Encoding and protocol reduce raw lane bandwidth",
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      "title": "Engineering example",
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      "title": "Distinctions and tradeoffs",
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      "id": "section-7",
      "title": "Specifications and interfaces",
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      "title": "Interfaces",
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      "title": "Check your understanding",
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      "id": "section-10",
      "title": "What happens if a fast PCIe device is connected through a slower supported host path?",
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      "title": "Sources",
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      "id": "section-13",
      "title": "Continue exploring",
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      "id": "section-14",
      "title": "Foundations",
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      "id": "section-15",
      "title": "Related lessons",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#pcie-interface"
    },
    {
      "title": "PCI-SIG: PCIe 5.0 signaling rates",
      "url": "https://pcisig.com/what-bit-rates-does-pcie-50-specification-support-and-how-does-it-compare-prior-pcie-generations"
    },
    {
      "title": "PCI-SIG: PCIe 6.0 FAQ",
      "url": "https://pcisig.com/faq?field_category_value%5B%5D=pci_express_6.0&keys=PAM4"
    },
    {
      "title": "Intel: PCI Express Gen4/Gen5 architecture and encoding",
      "url": "https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/004/pci-express-architecture/"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/pcie-interface-d5ac5ff5f0371444.json"
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    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
    },
    {
      "title": "Host CPU",
      "url": "https://semiaifoundry.com/learn/atlas/host-cpu/"
    },
    {
      "title": "Network interface adapter",
      "url": "https://semiaifoundry.com/learn/atlas/network-adapter/"
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    {
      "title": "NVMe solid-state storage",
      "url": "https://semiaifoundry.com/learn/atlas/nvme-storage/"
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    {
      "title": "Compute baseboard and tray",
      "url": "https://semiaifoundry.com/learn/atlas/compute-baseboard/"
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  "contentFormat": "text/markdown",
  "content": "Connectivity · Atlas v1.3.0\n\n# PCI Express interconnect\n\nConnects host processors, accelerators, storage, and network adapters through standardized serial links.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#pcie-interface)Centimeter board traces and connectors; logical lane pairs enlarged\n\nLearning objectiveKeep lane rate, encoding and byte rate in one boundary.\n\n## The mechanism\n\nPCIe is a general-purpose component interconnect built from serial lanes. A link can use several lanes in parallel, and switches can connect multiple devices into a hierarchy. Transactions carry commands and data; software uses drivers and device capabilities to arrange transfers. The generation and lane count must both be stated when comparing bandwidth. A faster endpoint may operate at a lower rate when the host, switch, or board path supports less. Transmit and receive paths contribute to different directional rates; packet overhead also separates a link rating from one-way application throughput. PCIe is one part of the AI system’s connectivity, alongside specialized coherent links, GPU scale-up fabrics, and the network between servers.\n\n1.  The endpoints train a link and agree on a supported speed and lane width.\n2.  Transactions are packetized and serialized across separate transmit and receive paths.\n3.  The receiving device handles requests or data and sends completions as required by the protocol.\n\n## Science and assumptions\n\n### Encoding and protocol reduce raw lane bandwidth\n\n$$\nB_{\\mathrm{Gen5,one\\ way}}=N_{\\mathrm{lanes}}\\,(32\\times10^9\\,\\mathrm{bits/s})\\frac{128}{130}\\frac{1\\,\\mathrm{byte}}{8\\,\\mathrm{bits}}\n$$\n\nGen5 one-way bandwidth equals lane count times 32 billion raw bits per second per lane, times the 128-over-130 encoding fraction, divided by eight bits per byte.\n\nSymbols and units\n\nB\\_Gen5,one way\n\nGen5 directional bandwidth after 128b/130b encoding\n\nbytes/s\n\nN\\_lanes\n\nNegotiated active lane count\n\nlanes\n\n32 × 10⁹ bits/s\n\nRaw per-lane NRZ bit rate corresponding to 32 GT/s\n\nbits/(s·lane)\n\n128/130\n\nEncoding payload fraction before transaction overhead\n\nfraction\n\nFor a Gen5 link, each lane runs at 32 GT/s with 128b/130b encoding. Sixteen lanes yield about 63.0 GB/s per direction after this encoding overhead, before transaction and link-protocol costs. Full-duplex operation can carry traffic both ways, but summing the directions does not make a single transfer twice as fast.\n\nAssumptions PCIe Gen5 at negotiated full lane width, using NRZ and 128b/130b encoding. Excludes packet headers, flow control, acknowledgments, and implementation limits. PCIe Gen6 uses a different signaling and FLIT model and must be calculated separately.\n\n## Engineering example\n\nA Gen5 x16 one-way payload estimate multiplies lanes, raw rate and 128/130 encoding efficiency, then divides bits by eight.\n\n## Distinctions and tradeoffs\n\nGT/s, GB/s, and bidirectional aggregate bandwidth are different measures. A raw line rate must account for lane count, direction, and protocol overhead before comparison with application throughput.\n\nHigher speeds increase transfer capacity but tighten electrical and board-design requirements. Real throughput also depends on packet overhead, topology, transfer size, and device behavior.\n\nNICs and NVMe drives use PCIe to deliver data into the compute system. Congestion on these paths can starve accelerators even when the GPUs themselves are fast.\n\n## Specifications and interfaces\n\nPCIe 5.0 signaling\n\n32 GT/s per lane\n\nRaw transfer rate; payload bandwidth is lower.\n\nPCIe 6.0 signaling\n\n64 GT/s per lane\n\nUses PAM4, FLIT encoding, and forward error correction.\n\nPCIe 6.0 ×16\n\n256 GB/s raw bidirectional\n\n128 GB/s each direction before protocol overhead; not a GB200 board-wide guarantee.\n\n### Interfaces\n\nHost transactions Input\n\nMemory reads/writes, commands, and completions\n\nDevice transfers Output\n\nDMA data and completion traffic\n\nLink training Input\n\nNegotiated width, speed, and signal equalization\n\n## Check your understanding\n\n### What happens if a fast PCIe device is connected through a slower supported host path?\n\n1.  The link must always use the device’s maximum advertised generation.\n2.  It operates at a mutually supported speed and width.\n3.  It automatically becomes an NVLink interface.\n\nAnswer and reasoning\n\nIt operates at a mutually supported speed and width.\n\nPCIe capability is negotiated across the actual link. The endpoint, host, switches, and board support determine what is usable.\n\n## Evidence and scope\n\nProtocol packets, flow control and platform limits reduce delivered throughput.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [PCI-SIG: PCIe 5.0 signaling rates](https://pcisig.com/what-bit-rates-does-pcie-50-specification-support-and-how-does-it-compare-prior-pcie-generations)\n-   [PCI-SIG: PCIe 6.0 FAQ](https://pcisig.com/faq?field_category_value%5B%5D=pci_express_6.0&keys=PAM4)\n-   [Intel: PCI Express Gen4/Gen5 architecture and encoding](https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/004/pci-express-architecture/)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/pcie-interface-d5ac5ff5f0371444.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n-   [Host CPU](https://semiaifoundry.com/learn/atlas/host-cpu/)\n\n### Related lessons\n\n-   [Network interface adapter](https://semiaifoundry.com/learn/atlas/network-adapter/)\n-   [NVMe solid-state storage](https://semiaifoundry.com/learn/atlas/nvme-storage/)\n-   [Compute baseboard and tray](https://semiaifoundry.com/learn/atlas/compute-baseboard/)"
}