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  "title": "PCIe and CXL: transport versus memory semantics",
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  "description": "Distinguishes peripheral data transfer from supported coherent memory operations.",
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  "revisionDate": "2026-10-07",
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  "topic": "Chip-to-hall integration",
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      "title": "PCIe and CXL: transport versus memory semantics",
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      "url": "https://semiaifoundry.com/ai-atlas/#pcie-cxl-semantics"
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      "title": "Compute Express Link 2.0 Specification Now Available",
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  "content": "Chip-to-hall integration · Atlas v1.3.0\n\n# PCIe and CXL: transport versus memory semantics\n\nDistinguishes peripheral data transfer from supported coherent memory operations.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#pcie-cxl-semantics)Micrometers of package wiring to board-scale links; schematic\n\nLearning objectiveExplain why physical transport, coherent semantics and memory performance are distinct.\n\n## The mechanism\n\nPCI Express provides a widely used physical and protocol foundation for host devices. CXL builds on a PCIe physical foundation while adding defined cache and memory semantics alongside I/O. This enables supported devices to participate in coherent access or expose memory through specific host/device roles. It does not make distant memory equivalent to local DRAM: requests still cross links, queues and controllers. Software, firmware and device generation determine what is actually enabled. Both the physical route and the ownership or coherence behavior matter: equal link rates do not imply identical programming semantics.\n\n1.  Identify host and device roles and the CXL version supported by both endpoints.\n2.  Separate ordinary I/O transactions from enabled cache or memory protocol operations.\n3.  Map memory ownership and address translation consistently across the system.\n4.  Trace requests through physical links and controllers despite a convenient software address model.\n5.  Measure the intended workload before treating expanded memory as a substitute for nearby capacity.\n\n## Science and assumptions\n\n### Two-tier access estimate\n\n$$\nL_{\\mathrm{avg}}=pL_{\\mathrm{near}}+(1-p)L_{\\mathrm{far}}\n$$\n\nAverage latency weights the near and far access latencies by their respective access fractions.\n\nSymbols and units\n\nL\\_avg\n\nMean access latency in the two-tier model\n\ns/access\n\np\n\nFraction of accesses using the near tier\n\nfraction\n\nL\\_near\n\nNear-tier access latency\n\ns/access\n\nL\\_far\n\nFar-tier access latency\n\ns/access\n\np is the near-access fraction and latency values are seconds/access.\n\nAssumptions Simple average without overlap or queueing; a dependent chain or tail metric needs additional analysis.\n\n## Engineering example\n\nSynthetic placement: moving a rarely accessed 10 GB table to a larger tier may free nearby memory for hot state. Moving a repeatedly streamed hot tensor can instead increase runtime despite identical total capacity.\n\n## Distinctions and tradeoffs\n\nCoherence supplies consistency rules; it does not erase physical distance or guarantee identical access cost.\n\nExpanded or shared memory can improve capacity utilization while exposing link latency and management complexity.\n\nModel state that does not fit near an accelerator may use a larger memory tier, but traffic-sensitive operations need a measured access budget.\n\n## Specifications and interfaces\n\nProtocol roles\n\nCXL.io, CXL.cache and CXL.mem\n\nSupported roles depend on device type and version.\n\nMemory expansion\n\nAdditional addressable capacity\n\nCapacity does not guarantee local-memory latency or bandwidth.\n\n### Interfaces\n\nHost requests Input\n\nI/O transactions or supported coherent memory operations\n\nDevice or attached memory Output\n\nCompletions, data and coherence responses\n\n## Check your understanding\n\n### What does adding CXL memory establish most directly?\n\n1.  Automatic HBM bandwidth for every request\n2.  An enabled additional memory resource with defined access semantics\n3.  The same latency as every CPU cache\n\nAnswer and reasoning\n\nAn enabled additional memory resource with defined access semantics\n\nActual access time and rate remain properties of the complete implemented path.\n\n## Evidence and scope\n\nCXL 2.0 is a historical teaching disclosure. No latest-generation support, universal latency or arbitrary platform compatibility is asserted.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Compute Express Link 2.0 Specification Now Available](https://computeexpresslink.org/blog/compute-express-link-2-0-specification-now-available-2374/)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/pcie-cxl-semantics-e6a6b492b501174a.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [PCI Express interconnect](https://semiaifoundry.com/learn/atlas/pcie-interface/)\n-   [DDR5 server memory](https://semiaifoundry.com/learn/atlas/ddr-memory/)\n\n### Related lessons\n\n-   [Die-to-die links and UCIe compatibility](https://semiaifoundry.com/learn/atlas/die-link-compatibility/)"
}