# Package substrate

Canonical: https://semiaifoundry.com/learn/atlas/package-substrate/
Revision: 2026-10-07
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Advanced packaging · Atlas v1.3.0

# Package substrate

Fans dense chip connections out to a mechanically supported interface with the circuit board.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#package-substrate)Centimeter-scale package with thin multilayer construction

Learning objectiveTurn an allowed voltage droop into an impedance budget.

## The mechanism

The package substrate is a multilayer wiring and support structure beneath the dies and their dense interconnect platform. It carries signals, power, and ground through patterned copper, insulating layers, and vias. The connection spacing grows as routes move from the die side toward the board side. Power and signal integrity depend on routing geometry and return paths, not simply on how many wires fit. The substrate also helps manage mechanical loads and must cope with different thermal expansion among silicon, copper, and organic materials. Signal traces and broad power planes have different electrical roles even when they share the same laminated substrate. This shows why the green or brown platform under a processor is an engineered electrical structure rather than passive packaging.

1.  Dense die-side connections enter a stack of copper routes, dielectric layers, and vias.
2.  Signal routes and power planes distribute connections across the package while preserving useful return paths and supply quality.
3.  Larger-pitch terminals connect the package to the board, and the substrate supports mechanical and thermal loads.

## Science and assumptions

### The supply path must stay below a target impedance

$$
Z_{\mathrm{target}}=\frac{\Delta V_{\mathrm{allowed}}}{\Delta I_{\mathrm{step}}}
$$

The impedance target is allowed voltage excursion divided by current-step magnitude.

Symbols and units

Z\_target

Target power-distribution impedance magnitude

Ω

ΔV\_allowed

Allowed voltage-excursion magnitude

V

ΔI\_step

Specified nonzero current-step magnitude

A

ΔVallowed is the permissible rail-voltage excursion and ΔIstep is a change in load current. Their ratio sets an impedance target for the power delivery network. The substrate, board planes, vias, capacitors, and regulator jointly determine whether that target can be approached over the relevant frequencies. A connection that looks adequate at DC may still have too much transient impedance.

Assumptions A design target derived from a specified load step and voltage tolerance, not a complete stability proof. Frequency-dependent inductance, resonances, control response, and package parasitics must be analyzed; no vendor rail tolerance is supplied.

## Engineering example

A 50 mV transient at 500 A implies a 100 μΩ target in the simplified boundary; loop inductance and frequency response still need analysis.

## Distinctions and tradeoffs

The substrate is not merely a mechanical platform. Its routing and power distribution affect signal integrity, supply stability, and usable system performance.

More routing layers and finer features can support larger systems but raise cost and fabrication demands. Electrical, thermal, and mechanical requirements must fit the same physical stack.

An accelerator requires both dense data links and a substantial supply of current. The substrate is the transition that makes the silicon usable as a board-level component.

## Specifications and interfaces

Common materials

Copper plus organic build-up dielectrics

Amkor describes laminate substrates including ABF and prepreg.

Vendor layer example

4–18 laminate build-up layers

Amkor flip-chip technology family; not a GB200 substrate specification.

Board interface

BGA or other module connection

Exact construction is product dependent.

### Interfaces

Die-side interface Input

Fine-pitch signals and supply distribution

Board-side interface Output

Larger-pitch electrical connections

Mechanical load Input

Mounting forces and thermal expansion

## Check your understanding

### Why are signal and power views both needed to understand the substrate?

1.  They are unrelated decorations on the same drawing.
2.  Every route carries both signals and coolant.
3.  The package must move information and deliver substantial electrical current.

Answer and reasoning

The package must move information and deliver substantial electrical current.

Signal traces and power networks serve different functions, but both must fit within the same mechanically reliable multilayer structure.

## Evidence and scope

The boundary excludes package and board parasitics unless included in $Z_{\mathrm{target}}$.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [Amkor Flip Chip technology sheet](https://amkor.com/cn/wp-content/uploads/2018/02/Flip_Chip_TS102.pdf)
-   [Amkor flip chip CSP materials data sheet](https://amkor.com/wp-content/uploads/2018/02/fcCSP_DS577.pdf)
-   [Intel Power Delivery Network Tool User Guide](https://cdrdv2-public.intel.com/655157/ug_pdn.pdf)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/package-substrate-514c062ea3b682bd.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)
-   [Microbumps and bonding joints](https://semiaifoundry.com/learn/atlas/microbump/)

### Related lessons

-   [Interposer and redistribution layers](https://semiaifoundry.com/learn/atlas/interposer/)
-   [Compute baseboard and tray](https://semiaifoundry.com/learn/atlas/compute-baseboard/)
-   [Voltage regulator module](https://semiaifoundry.com/learn/atlas/voltage-regulator/)