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  "id": "atlas-lesson-package-substrate",
  "title": "Package substrate",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Fans dense chip connections out to a mechanically supported interface with the circuit board.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Advanced packaging",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "The boundary excludes package and board parasitics unless included in Z_target.",
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  "artifactUrl": "https://semiaifoundry.com/ai-atlas/lesson-data/package-substrate-514c062ea3b682bd.json",
  "interactiveUrl": "https://semiaifoundry.com/ai-atlas/#package-substrate",
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  "markdownUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-package-substrate.md",
  "sections": [
    {
      "id": "section-1",
      "title": "Package substrate",
      "start": 35,
      "end": 359
    },
    {
      "id": "section-2",
      "title": "The mechanism",
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      "end": 1522
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    {
      "id": "section-3",
      "title": "Science and assumptions",
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    {
      "id": "section-4",
      "title": "The supply path must stay below a target impedance",
      "start": 1550,
      "end": 2622
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    {
      "id": "section-5",
      "title": "Engineering example",
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      "id": "section-6",
      "title": "Distinctions and tradeoffs",
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    {
      "id": "section-7",
      "title": "Specifications and interfaces",
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      "id": "section-8",
      "title": "Interfaces",
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      "id": "section-9",
      "title": "Check your understanding",
      "start": 3931,
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    {
      "id": "section-10",
      "title": "Why are signal and power views both needed to understand the substrate?",
      "start": 3960,
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      "title": "Evidence and scope",
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      "id": "section-12",
      "title": "Sources",
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    {
      "id": "section-13",
      "title": "Continue exploring",
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      "id": "section-14",
      "title": "Foundations",
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      "end": 5500
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      "id": "section-15",
      "title": "Related lessons",
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      "end": 5794
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#package-substrate"
    },
    {
      "title": "Amkor Flip Chip technology sheet",
      "url": "https://amkor.com/cn/wp-content/uploads/2018/02/Flip_Chip_TS102.pdf"
    },
    {
      "title": "Amkor flip chip CSP materials data sheet",
      "url": "https://amkor.com/wp-content/uploads/2018/02/fcCSP_DS577.pdf"
    },
    {
      "title": "Intel Power Delivery Network Tool User Guide",
      "url": "https://cdrdv2-public.intel.com/655157/ug_pdn.pdf"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/package-substrate-514c062ea3b682bd.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
    },
    {
      "title": "Microbumps and bonding joints",
      "url": "https://semiaifoundry.com/learn/atlas/microbump/"
    },
    {
      "title": "Interposer and redistribution layers",
      "url": "https://semiaifoundry.com/learn/atlas/interposer/"
    },
    {
      "title": "Compute baseboard and tray",
      "url": "https://semiaifoundry.com/learn/atlas/compute-baseboard/"
    },
    {
      "title": "Voltage regulator module",
      "url": "https://semiaifoundry.com/learn/atlas/voltage-regulator/"
    }
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  "contentFormat": "text/markdown",
  "content": "Advanced packaging · Atlas v1.3.0\n\n# Package substrate\n\nFans dense chip connections out to a mechanically supported interface with the circuit board.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#package-substrate)Centimeter-scale package with thin multilayer construction\n\nLearning objectiveTurn an allowed voltage droop into an impedance budget.\n\n## The mechanism\n\nThe package substrate is a multilayer wiring and support structure beneath the dies and their dense interconnect platform. It carries signals, power, and ground through patterned copper, insulating layers, and vias. The connection spacing grows as routes move from the die side toward the board side. Power and signal integrity depend on routing geometry and return paths, not simply on how many wires fit. The substrate also helps manage mechanical loads and must cope with different thermal expansion among silicon, copper, and organic materials. Signal traces and broad power planes have different electrical roles even when they share the same laminated substrate. This shows why the green or brown platform under a processor is an engineered electrical structure rather than passive packaging.\n\n1.  Dense die-side connections enter a stack of copper routes, dielectric layers, and vias.\n2.  Signal routes and power planes distribute connections across the package while preserving useful return paths and supply quality.\n3.  Larger-pitch terminals connect the package to the board, and the substrate supports mechanical and thermal loads.\n\n## Science and assumptions\n\n### The supply path must stay below a target impedance\n\n$$\nZ_{\\mathrm{target}}=\\frac{\\Delta V_{\\mathrm{allowed}}}{\\Delta I_{\\mathrm{step}}}\n$$\n\nThe impedance target is allowed voltage excursion divided by current-step magnitude.\n\nSymbols and units\n\nZ\\_target\n\nTarget power-distribution impedance magnitude\n\nΩ\n\nΔV\\_allowed\n\nAllowed voltage-excursion magnitude\n\nV\n\nΔI\\_step\n\nSpecified nonzero current-step magnitude\n\nA\n\nΔVallowed is the permissible rail-voltage excursion and ΔIstep is a change in load current. Their ratio sets an impedance target for the power delivery network. The substrate, board planes, vias, capacitors, and regulator jointly determine whether that target can be approached over the relevant frequencies. A connection that looks adequate at DC may still have too much transient impedance.\n\nAssumptions A design target derived from a specified load step and voltage tolerance, not a complete stability proof. Frequency-dependent inductance, resonances, control response, and package parasitics must be analyzed; no vendor rail tolerance is supplied.\n\n## Engineering example\n\nA 50 mV transient at 500 A implies a 100 μΩ target in the simplified boundary; loop inductance and frequency response still need analysis.\n\n## Distinctions and tradeoffs\n\nThe substrate is not merely a mechanical platform. Its routing and power distribution affect signal integrity, supply stability, and usable system performance.\n\nMore routing layers and finer features can support larger systems but raise cost and fabrication demands. Electrical, thermal, and mechanical requirements must fit the same physical stack.\n\nAn accelerator requires both dense data links and a substantial supply of current. The substrate is the transition that makes the silicon usable as a board-level component.\n\n## Specifications and interfaces\n\nCommon materials\n\nCopper plus organic build-up dielectrics\n\nAmkor describes laminate substrates including ABF and prepreg.\n\nVendor layer example\n\n4–18 laminate build-up layers\n\nAmkor flip-chip technology family; not a GB200 substrate specification.\n\nBoard interface\n\nBGA or other module connection\n\nExact construction is product dependent.\n\n### Interfaces\n\nDie-side interface Input\n\nFine-pitch signals and supply distribution\n\nBoard-side interface Output\n\nLarger-pitch electrical connections\n\nMechanical load Input\n\nMounting forces and thermal expansion\n\n## Check your understanding\n\n### Why are signal and power views both needed to understand the substrate?\n\n1.  They are unrelated decorations on the same drawing.\n2.  Every route carries both signals and coolant.\n3.  The package must move information and deliver substantial electrical current.\n\nAnswer and reasoning\n\nThe package must move information and deliver substantial electrical current.\n\nSignal traces and power networks serve different functions, but both must fit within the same mechanically reliable multilayer structure.\n\n## Evidence and scope\n\nThe boundary excludes package and board parasitics unless included in $Z_{\\mathrm{target}}$.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Amkor Flip Chip technology sheet](https://amkor.com/cn/wp-content/uploads/2018/02/Flip_Chip_TS102.pdf)\n-   [Amkor flip chip CSP materials data sheet](https://amkor.com/wp-content/uploads/2018/02/fcCSP_DS577.pdf)\n-   [Intel Power Delivery Network Tool User Guide](https://cdrdv2-public.intel.com/655157/ug_pdn.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/package-substrate-514c062ea3b682bd.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n-   [Microbumps and bonding joints](https://semiaifoundry.com/learn/atlas/microbump/)\n\n### Related lessons\n\n-   [Interposer and redistribution layers](https://semiaifoundry.com/learn/atlas/interposer/)\n-   [Compute baseboard and tray](https://semiaifoundry.com/learn/atlas/compute-baseboard/)\n-   [Voltage regulator module](https://semiaifoundry.com/learn/atlas/voltage-regulator/)"
}