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  "title": "NVMe solid-state storage",
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  "description": "Persists datasets, model checkpoints, and software beyond power cycles.",
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  "revisionDate": "2026-10-07",
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  "topic": "Host platform",
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      "title": "NVMe solid-state storage",
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      "title": "Why is a saved checkpoint useful after a node loses power?",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#nvme-storage"
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    {
      "title": "Micron 9550 NVMe data center SSD",
      "url": "https://www.micron.com/products/storage/ssd/data-center-ssd/9550-ssd"
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    {
      "title": "Micron 9550 SSD technical product specification",
      "url": "https://www.micron.com/content/dam/micron/global/public/products/data-sheet/ssd/9550-nvme-ssd-tech-prod-spec.pdf"
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    {
      "title": "John D. C. Little (2011): Little’s Law and computer architecture applications",
      "url": "https://pubsonline.informs.org/doi/pdf/10.1287/opre.1110.0940"
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      "title": "PCI Express interconnect",
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  "content": "Host platform · Atlas v1.3.0\n\n# NVMe solid-state storage\n\nPersists datasets, model checkpoints, and software beyond power cycles.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#nvme-storage)Centimeter-scale module containing controller and NAND packages\n\nLearning objectiveUse Little’s law to relate average outstanding I/O, throughput and latency within one storage boundary.\n\n## The mechanism\n\nAn NVMe SSD combines nonvolatile NAND flash, a controller, firmware, and a fast host interface. It stores data persistently rather than providing the byte-addressable working memory used directly by arithmetic units. The controller maps logical blocks to flash locations, handles error management, and schedules reads and writes across internal parallelism. Large sequential transfers and small random accesses stress different parts of the device, so one speed number cannot describe every workload. Loading a checkpoint moves persistent data into working memory; repeated tensor computation then uses that working state, with different access and lifetime requirements. Supported direct-storage paths can reduce extra copies, but the storage device still has its own latency, bandwidth, and endurance limits.\n\n1.  The host issues block requests through the NVMe protocol to the SSD controller.\n2.  The controller maps those requests onto flash operations and uses internal parallelism and error handling to read or write data.\n3.  Data are loaded into working memory for computation, while completed checkpoints can be committed back to persistent storage.\n\n## Science and assumptions\n\n### High IOPS requires enough outstanding work\n\n$$\n\\mathrm{QD}_{\\mathrm{average}}\\approx\\mathrm{IOPS}\\,L_{\\mathrm{average}}\n$$\n\nAverage queue depth is approximately completed operations per second times average operation latency.\n\nSymbols and units\n\nQD\\_average\n\nAverage operations in flight\n\noperations\n\nIOPS\n\nCompleted I/O operation rate\n\noperations/s\n\nL\\_average\n\nMean operation latency at the same boundary\n\ns\n\nQueue depth is the average number of operations in flight, IOPS is completed operations per second, and L is average latency in seconds. A drive capable of high throughput can remain underused if the application submits one request and waits before issuing the next. Increasing concurrency helps only until the storage, host link, or workload becomes the bottleneck.\n\nAssumptions Little’s law applied to a stable workload with a consistent measurement boundary. Latency generally changes with load, so the relation does not promise constant latency at arbitrary queue depth; read size, write mix, and durability requirements matter.\n\n## Engineering example\n\nSynthetic stable workload: 100,000 IOPS at 200 μs average latency implies 100,000 × 0.0002 = 20 average outstanding operations. Doubling submitted queue depth does not imply double IOPS, because latency and the limiting resource may also change.\n\n## Distinctions and tradeoffs\n\nNVMe storage capacity is not interchangeable with HBM capacity. Storage persists without power but has a different access model and much higher access cost.\n\nStorage offers durable capacity but is far slower than on-chip memory and HBM. Checkpoint frequency trades recovery effort against write traffic and interruption to useful work.\n\nTraining begins with stored data and produces checkpoints that must survive failures. Serving systems also need to load and update model artifacts reliably.\n\n## Specifications and interfaces\n\nMicron 9550 example\n\nUp to 14.0 GB/s sequential read\n\nVendor-rated maximum; capacity, host, and test conditions matter.\n\nSequential write\n\nUp to 10.0 GB/s\n\nMicron 9550 selected configurations; not all capacities reach this.\n\nHost protocol\n\nNVMe over PCIe Gen5\n\nThe protocol and physical interface are distinct layers.\n\n### Interfaces\n\nRead/write commands Input\n\nLogical block requests\n\nPersistent data Output\n\nDataset batches, model files, and checkpoints\n\nCheckpoint writes Input\n\nTraining state committed for recovery\n\n## Check your understanding\n\n### Why is a saved checkpoint useful after a node loses power?\n\n1.  It remains in a powered-off GPU register.\n2.  It changes the physical number of Tensor Cores.\n3.  A nonvolatile storage copy survives when volatile working memory is lost.\n\nAnswer and reasoning\n\nA nonvolatile storage copy survives when volatile working memory is lost.\n\nCheckpoints persist the state needed for recovery. Their usefulness depends on what was saved and how recently it was committed.\n\n## Evidence and scope\n\nThis is a steady-state queueing identity applied to the storage boundary, as explained by the lesson. I/O size, read/write mix, persistence requirements and latency definition must match; no product performance is inferred.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Micron 9550 NVMe data center SSD](https://www.micron.com/products/storage/ssd/data-center-ssd/9550-ssd)\n-   [Micron 9550 SSD technical product specification](https://www.micron.com/content/dam/micron/global/public/products/data-sheet/ssd/9550-nvme-ssd-tech-prod-spec.pdf)\n-   [John D. C. Little (2011): Little’s Law and computer architecture applications](https://pubsonline.informs.org/doi/pdf/10.1287/opre.1110.0940)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/nvme-storage-47d41592ea665d95.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [PCI Express interconnect](https://semiaifoundry.com/learn/atlas/pcie-interface/)\n\n### Related lessons\n\n-   [Host CPU](https://semiaifoundry.com/learn/atlas/host-cpu/)\n-   [Compute baseboard and tray](https://semiaifoundry.com/learn/atlas/compute-baseboard/)\n-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)"
}