# Nanosheet release and replacement gates

Canonical: https://semiaifoundry.com/learn/atlas/nanosheet-gate-last-integration/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Fabrication / FEOL and MOL · Atlas v1.3.0

# Nanosheet release and replacement gates

Creates channels that can be surrounded by a gate after sacrificial materials are removed.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#nanosheet-gate-last-integration)Nanometer device cross-sections; reference flow with alternatives

Learning objectiveTrace retained and sacrificial materials through a representative gate-last nanosheet sequence.

## The mechanism

A stacked nanosheet transistor begins with layers that have different jobs. Some become channels; others provide temporary spacing and can later be removed selectively. A representative replacement-gate route uses a temporary gate while spacers and source/drain structures are formed. After opening the gate region, a selective release exposes channel surfaces so a dielectric and metal gate can surround them. Inner spacers help separate the gate from source/drain regions. Every operation must preserve thin channels and compatible interfaces. The animation labels retained and sacrificial materials throughout, making it clear that the final empty spaces were engineered into the starting stack.

1.  Grow and pattern an alternating stack whose material contrast supports later selective removal.
2.  Use a temporary gate and spacers to establish the region for subsequent replacement.
3.  Form source/drain and inner-spacer features while maintaining channel support and isolation.
4.  Remove temporary gate material and selectively release sacrificial layers without unacceptable channel loss.
5.  Deposit gate dielectric and conductors around the accessible channels, then inspect fill and electrical behavior.

## Science and assumptions

### Channel-loss budget

$$
\Delta t_{\mathrm{channel}}\approx\frac{h_{\mathrm{removed}}}{S}
$$

Channel thickness loss is approximately sacrificial removal distance divided by sacrificial-to-channel selectivity.

Symbols and units

Δt\_channel

Channel-material thickness lost in the toy selectivity budget

nm

h\_removed

Representative sacrificial-material removal distance

nm

S

Sacrificial-to-channel etch-rate selectivity

dimensionless rate ratio

$h_{\mathrm{removed}}$ is a representative sacrificial removal distance and S the sacrificial-to-channel etch selectivity; lengths match.

Assumptions A simplified selectivity budget. Three-dimensional transport, crystal surfaces, nonuniformity and overetch make actual release more complex.

## Engineering example

Synthetic budget: 20 nm equivalent sacrificial removal at selectivity 100 predicts 0.2 nm channel loss before nonuniformity and overetch. At atomic-scale channel dimensions, even that estimate is consequential.

## Distinctions and tradeoffs

Channels are not individually placed into the final gate cavity like loose mechanical shelves.

More channels can increase drive per footprint but complicate release, gate fill, parasitics and thermal/process control.

Gate-all-around integration is one route for sustaining logic density and electrostatic control as devices become harder to scale.

## Specifications and interfaces

Material roles

Retained channel vs sacrificial layer

Color denotes function; no universal layer thickness is implied.

Gate access

Surrounding released channel surfaces

Conformal film access and selective removal are distinct requirements.

### Interfaces

Alternating epitaxial stack Input

Designed channel and sacrificial layers

Completed gate-all-around region Output

Supported channels with dielectric and metal surrounding them

## Check your understanding

### Why is selective removal central to a nanosheet replacement-gate route?

1.  It replaces all testing
2.  It exposes retained channel surfaces without removing the channels
3.  It removes every semiconductor layer

Answer and reasoning

It exposes retained channel surfaces without removing the channels

The alternating stack provides material contrast so the temporary spacing layers can be removed while useful channels remain.

## Evidence and scope

Applied Materials describes representative operations; the atlas does not claim a complete foundry recipe. The selectivity example is synthetic.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [Applied Materials — New Ways to Shrink](https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc)
-   [imec — CMOS scaling](https://www.imec-int.com/en/expertise/cmos-advanced/compute/cmos-scaling)
-   [IBM Research — Stacked nanosheet gate-all-around transistor](https://research.ibm.com/publications/stacked-nanosheet-gate-all-around-transistor-to-enable-scaling-beyond-finfet)
-   [Intel — High-k and metal-gate transistor announcement](https://www.intel.com/pressroom/archive/releases/2007/20070128comp.htm)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/nanosheet-gate-last-integration-3c63a93d2d9cc31d.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Gate-all-around nanosheet transistor](https://semiaifoundry.com/learn/atlas/gaa/)
-   [Epitaxy and engineered starting layers](https://semiaifoundry.com/learn/atlas/epitaxial-material-stack/)
-   [Plasma and wet etch: selectivity and profile](https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/)

### Related lessons

-   [ALD and self-limiting surface reactions](https://semiaifoundry.com/learn/atlas/ald-self-limiting-growth/)
-   [Source/drain, spacers, contacts and MOL](https://semiaifoundry.com/learn/atlas/source-drain-contact-integration/)