{
  "schemaVersion": 1,
  "id": "atlas-lesson-nand",
  "title": "Two-input CMOS NAND gate",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Implements a universal Boolean operation with complementary transistor networks.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/nand/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Digital circuits",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "This is ideal Boolean reasoning within valid voltage ranges, using the linked computation-structures treatment. It does not predict transition current, delay or simultaneous conduction.",
  "contentCoverage": "published-lesson",
  "artifactUrl": "https://semiaifoundry.com/ai-atlas/lesson-data/nand-608a6195e37226ae.json",
  "interactiveUrl": "https://semiaifoundry.com/ai-atlas/#nand",
  "related": [],
  "supersedes": [],
  "supersededBy": [],
  "contentHash": "9803466276e524bd5e125a1eafeab6fcdc5d92773d671e81aa599ea70eb9a0a3",
  "contentLength": 4275,
  "jsonUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-nand.json",
  "markdownUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-nand.md",
  "sections": [
    {
      "id": "section-1",
      "title": "Two-input CMOS NAND gate",
      "start": 33,
      "end": 359
    },
    {
      "id": "section-2",
      "title": "The mechanism",
      "start": 359,
      "end": 1289
    },
    {
      "id": "section-3",
      "title": "Science and assumptions",
      "start": 1289,
      "end": 1317
    },
    {
      "id": "section-4",
      "title": "Boolean function from topology",
      "start": 1317,
      "end": 1886
    },
    {
      "id": "section-5",
      "title": "Engineering example",
      "start": 1886,
      "end": 2152
    },
    {
      "id": "section-6",
      "title": "Distinctions and tradeoffs",
      "start": 2152,
      "end": 2560
    },
    {
      "id": "section-7",
      "title": "Specifications and interfaces",
      "start": 2560,
      "end": 2813
    },
    {
      "id": "section-8",
      "title": "Interfaces",
      "start": 2813,
      "end": 2910
    },
    {
      "id": "section-9",
      "title": "Check your understanding",
      "start": 2910,
      "end": 2939
    },
    {
      "id": "section-10",
      "title": "When is a two-input NAND output zero?",
      "start": 2939,
      "end": 3232
    },
    {
      "id": "section-11",
      "title": "Evidence and scope",
      "start": 3232,
      "end": 3611
    },
    {
      "id": "section-12",
      "title": "Sources",
      "start": 3611,
      "end": 3948
    },
    {
      "id": "section-13",
      "title": "Continue exploring",
      "start": 3948,
      "end": 3971
    },
    {
      "id": "section-14",
      "title": "Foundations",
      "start": 3971,
      "end": 4072
    },
    {
      "id": "section-15",
      "title": "Related lessons",
      "start": 4072,
      "end": 4275
    }
  ],
  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#nand"
    },
    {
      "title": "MIT 6.004 — Computation Structures Student Notes",
      "url": "https://6191.mit.edu/_static/fall24/resources/references/6004_student_notes_FA20.pdf"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/nand-608a6195e37226ae.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "Complementary CMOS inverter",
      "url": "https://semiaifoundry.com/learn/atlas/inverter/"
    },
    {
      "title": "Full adder and carry network",
      "url": "https://semiaifoundry.com/learn/atlas/adder/"
    },
    {
      "title": "Standard-cell library and physical design",
      "url": "https://semiaifoundry.com/learn/atlas/standard-cell/"
    }
  ],
  "recordHash": "74661e3e6cc02ce522a57c739bed10a384a951afb3f852fcbd3e60c7eaf40a69",
  "contentFormat": "text/markdown",
  "content": "Digital circuits · Atlas v1.3.0\n\n# Two-input CMOS NAND gate\n\nImplements a universal Boolean operation with complementary transistor networks.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#nand)Microscopic four-device teaching cell\n\nLearning objectiveUse the series pull-down and parallel pull-up networks to construct a two-input NAND truth table.\n\n## The mechanism\n\nA two-input NAND outputs zero only when both inputs are one. Its standard static CMOS network uses series nMOS devices to pull down when both conditions are true and parallel pMOS devices to pull up otherwise. This relationship between series, parallel, and logic is the bridge from circuit topology to a truth table. NAND is universal: networks of NAND gates can represent any Boolean function, although practical chips use many cell types for efficiency. The atlas lets a viewer trace the conducting path for each input combination. Four visible devices are enough to explain the function, while the circuit's delay still depends on physical loads and transistor choices.\n\n1.  Use two series nMOS devices for the path from output to ground.\n2.  Use the complementary parallel pMOS network for the path toward the supply.\n3.  Evaluate input combinations: only two high inputs complete the pull-down condition.\n\n## Science and assumptions\n\n### Boolean function from topology\n\n$$\nY=\\neg(A\\land B)\n$$\n\nThe output is the logical negation of A AND B: it is low only when both inputs are high.\n\nSymbols and units\n\nY\n\nNAND output logic value\n\nBoolean\n\nA\n\nFirst input logic value\n\nBoolean\n\nB\n\nSecond input logic value\n\nBoolean\n\nSeries pull-down devices implement the requirement that both inputs be high. Their complementary parallel pull-up network produces the opposite output state.\n\nAssumptions Ideal logic values within valid input/output voltage ranges; real transition timing and analog current are omitted.\n\n## Engineering example\n\nWorked ideal truth table: inputs 00, 01 and 10 each leave at least one pull-up conducting and produce Y = 1. Input 11 enables the complete series pull-down and produces Y = 0. Thus three of the four input combinations produce a high output.\n\n## Distinctions and tradeoffs\n\nNAND universality means networks can express any Boolean function; it does not mean one NAND gate performs every computation.\n\nSeries devices add resistance to a conducting path. More complex cells trade transistor count against logic depth.\n\nNAND networks help implement control and arithmetic. Their composition explains how a few switching patterns scale into computation.\n\n## Specifications and interfaces\n\nLogic equation\n\nY = NOT(A AND B)\n\nOutput is low only for A = B = 1.\n\nCanonical implementation\n\n4 transistors\n\nTwo nMOS and two pMOS.\n\nLogical property\n\nUniversal gate\n\nNetworks can express arbitrary Boolean functions.\n\n### Interfaces\n\nA and B Input\n\nTwo binary-encoded voltage inputs\n\nY Output\n\nNAND output voltage\n\n## Check your understanding\n\n### When is a two-input NAND output zero?\n\n1.  Only when both inputs are one\n2.  Whenever either input is zero\n3.  For all input combinations\n\nAnswer and reasoning\n\nOnly when both inputs are one\n\nThe series pull-down devices conduct together for the two-high case, implementing NOT(A AND B).\n\n## Evidence and scope\n\nThis is ideal Boolean reasoning within valid voltage ranges, using the linked computation-structures treatment. It does not predict transition current, delay or simultaneous conduction.\n\nUse the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.\n\n## Sources\n\n-   [MIT 6.004 — Computation Structures Student Notes](https://6191.mit.edu/_static/fall24/resources/references/6004_student_notes_FA20.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/nand-608a6195e37226ae.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Complementary CMOS inverter](https://semiaifoundry.com/learn/atlas/inverter/)\n\n### Related lessons\n\n-   [Full adder and carry network](https://semiaifoundry.com/learn/atlas/adder/)\n-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)"
}