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  "title": "Binary multiplier and partial-product reduction",
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  "description": "Builds a product by generating and combining weighted partial products.",
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  "revisionDate": "2026-10-07",
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  "topic": "Arithmetic circuits",
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      "title": "Binary multiplier and partial-product reduction",
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      "title": "How wide can the full unsigned result of 4-bit × 4-bit multiplication be?",
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    {
      "title": "UC Berkeley EECS 151 — Adders II and Array Multipliers",
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      "title": "Full adder and carry network",
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    {
      "title": "Multiply–accumulate and fused arithmetic",
      "url": "https://semiaifoundry.com/learn/atlas/mac/"
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      "title": "Edge-triggered D flip-flop",
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  "content": "Arithmetic circuits · Atlas v1.3.0\n\n# Binary multiplier and partial-product reduction\n\nBuilds a product by generating and combining weighted partial products.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#multiplier)Small arithmetic block; 4 × 4 bit example is conceptual\n\nLearning objectiveAssemble an unsigned binary product from shifted partial products.\n\n## The mechanism\n\nAn unsigned binary multiplier starts with partial products formed from pairs of operand bits. Each partial product has a binary position, so the hardware must combine aligned contributions and carries. An array or reduction tree organizes that work; a final addition resolves the remaining result. Signed and floating-point multiplication require additional representation-specific machinery beyond this teaching example. The atlas arranges partial products in a shifted grid and highlights their reduction paths, revealing why multiplication has more structure than one isolated gate. Pipeline registers may separate stages so several products are in flight together. The shown four-bit example is deliberately small enough to inspect while preserving the dependency pattern of wider arithmetic.\n\n1.  Generate bit-pair partial products at their proper binary positions.\n2.  Reduce the aligned contributions through an array or tree of arithmetic logic.\n3.  Use final addition and representation handling to obtain the product.\n\n## Science and assumptions\n\n### Binary product expansion\n\n$$\nA B=\\sum_i\\sum_j(a_i b_j)2^{i+j}\n$$\n\nAn unsigned binary product is the sum of every bit-pair product weighted by two raised to the sum of the bit positions.\n\nSymbols and units\n\nA\n\nFirst unsigned binary operand\n\ninteger\n\nB\n\nSecond unsigned binary operand\n\ninteger\n\naᵢ\n\nBit i of A\n\n0 or 1\n\nbⱼ\n\nBit j of B\n\n0 or 1\n\ni,j\n\nFinite operand bit positions\n\nnonnegative integer indices\n\nEach pair of input bits contributes a weighted partial product. The array or tree reduces these contributions into the final binary result.\n\nAssumptions Unsigned finite binary operands; signed encodings and floating-point arithmetic require additional transformations.\n\n## Engineering example\n\nWorked multiplication: 0101₂ × 0011₂ forms 00000101₂ and 00001010₂ from the two set bits of the multiplier. Adding them gives 00001111₂ = 15. Four-bit unsigned operands need up to eight result bits because 15 × 15 = 225.\n\n## Distinctions and tradeoffs\n\nThe four-by-four partial-product example is not a claim about a commercial accelerator’s internal arithmetic width.\n\nParallel reduction improves throughput and delay. Wider arithmetic increases area, wiring, and switching activity.\n\nMultiplication is central to neural-network linear algebra. Its physical cost helps motivate lower-precision formats when accuracy permits.\n\n## Specifications and interfaces\n\nTeaching operands\n\n4 bits × 4 bits\n\nUnsigned illustrative example.\n\nFull result width\n\nUp to 8 bits\n\nExact product of two four-bit unsigned values.\n\nCore pattern\n\nPartial products → reduction → sum\n\nSpecific architectures choose different reductions.\n\n### Interfaces\n\nTwo operands Input\n\nBinary-encoded numbers\n\nProduct Output\n\nWeighted combination of partial products\n\n## Check your understanding\n\n### How wide can the full unsigned result of 4-bit × 4-bit multiplication be?\n\n1.  4 bits in every case\n2.  8 bits\n3.  16 bytes in every case\n\nAnswer and reasoning\n\n8 bits\n\nThe maximum product is 15 × 15 = 225, which requires eight bits to represent exactly.\n\n## Evidence and scope\n\nThis is the unsigned partial-product construction in the linked multiplier lecture. Signed encodings, floating-point normalization and circuit timing require additional rules.\n\nInspect row–column products and accumulated results in a small integer matrix; this does not simulate the individual gate network.\n\n## Sources\n\n-   [UC Berkeley EECS 151 — Adders II and Array Multipliers](https://www-inst.eecs.berkeley.edu/~eecs151/fa21/files/lectures/Lecture18-Adders2-2up.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/multiplier-4592de6e4971de75.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Full adder and carry network](https://semiaifoundry.com/learn/atlas/adder/)\n\n### Related lessons\n\n-   [Multiply–accumulate and fused arithmetic](https://semiaifoundry.com/learn/atlas/mac/)\n-   [Edge-triggered D flip-flop](https://semiaifoundry.com/learn/atlas/flipflop/)"
}