# Microbumps and bonding joints Canonical: https://semiaifoundry.com/learn/atlas/microbump/ Revision: 2026-10-07 Rights: https://semiaifoundry.com/ai-atlas/licenses.html Advanced packaging · Atlas v1.3.0 # Microbumps and bonding joints Join matching electrical terminals at the surfaces of dies and package interconnect layers. [Explore in Atlas](https://semiaifoundry.com/ai-atlas/#microbump)Tens-of-micrometers pitch class in advanced examples; schematic joints Learning objectiveConnect pitch and interface area to site count. ## The mechanism Microbumps are small conductive joints arranged in dense arrays. They connect one surface to another, such as a die to an interposer or adjacent memory layers. The surrounding underfill helps support the assembly and manage stress from materials expanding differently with temperature. A bump joins mating surfaces, while a TSV routes through silicon; the two can meet at a joint but remain different structures. Finer pitch supports more connections in a given area, yet raises demands on alignment, planarity, cleanliness, and defect control. A signal crosses a joint between matching pads, and an array of such joints supplies many connections when the mating components are assembled. 1. Matching terminals are formed on the surfaces that will be joined, using a connection pitch appropriate to the package process. 2. Alignment and bonding create conductive joints between the surfaces. 3. Underfill and surrounding structures support the joint array as the assembly heats, cools, and experiences mechanical stress. ## Science and assumptions ### Pitch controls the connection budget $$ N_{\mathrm{sites}}\approx\frac{A_{\mathrm{interface}}}{p^2} $$ The ideal joint-site count is usable interface area divided by pitch squared. Symbols and units N\_sites Potential joint sites in an ideal square array sites A\_interface Usable bonding area μm² p Square-array pitch μm Ainterface is usable bonding area and p is square-array pitch. Halving the pitch ideally quadruples the number of available connection sites in the same area. Some sites carry data while others provide clocks, control, power, and ground, so total joint count is not equal to interface data width. Finer pitch also reduces alignment and defect tolerances. Assumptions Ideal square array without edge losses, keep-outs, unequal pitches, missing joints, or power-routing constraints. It is a geometric upper estimate and does not assert a Blackwell bump count or pitch. ## Engineering example Halving pitch can increase ideal site count by roughly four for the same interface area, while assembly tolerance and current density become harder. ## Distinctions and tradeoffs A microbump joins two surfaces; a TSV passes through silicon. They may connect in series but are not the same structure. Finer joints improve connection density but leave less tolerance for manufacturing variation. Reliable assembly must survive both initial bonding and repeated thermal cycles. High-bandwidth packages need many simultaneous electrical connections. Tiny bonding joints make that dense connectivity possible between separately fabricated components. ## Specifications and interfaces Assembly form Dense arrays of conductive joints Materials and exact pitch depend on the package technology. Published pitch example 40 µm minimum I/O pitch TSMC InFO\_oS platform example; not an asserted Blackwell microbump pitch. Mechanical support Underfill between joined surfaces Common flip-chip construction; process differs by vendor. ### Interfaces Upper terminal Input Electrical signal or supply Bonded joint Output Current crossing between surfaces Underfill contact Input Mechanical support around the joint ## Check your understanding ### Why is a finer bump pitch useful? 1. It fits more electrical connections into a given surface area. 2. It removes the need to align the surfaces. 3. It directly increases the number of software model layers. Answer and reasoning It fits more electrical connections into a given surface area. Connection density enables wider interfaces and more integration, but finer spacing also tightens manufacturing tolerances. ## Evidence and scope Not every site is usable; keep-outs, power and test access reduce the count. Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism. ## Sources - [TSMC InFO packaging: published interconnect examples](https://www.tsmc.com/english/dedicatedFoundry/technology/InFO) - [Amkor flip chip CSP materials data sheet](https://amkor.com/wp-content/uploads/2018/02/fcCSP_DS577.pdf) [Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/microbump-52be9232f9ddf053.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html) ## Continue exploring ### Foundations - [Device contact and interface resistance](https://semiaifoundry.com/learn/atlas/contact/) - [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/) ### Related lessons - [Through-silicon via](https://semiaifoundry.com/learn/atlas/through-silicon-via/) - [Interposer and redistribution layers](https://semiaifoundry.com/learn/atlas/interposer/) - [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/) - [Package substrate](https://semiaifoundry.com/learn/atlas/package-substrate/)