# Choosing SRAM, HBM, DDR, LPDDR or GDDR

Canonical: https://semiaifoundry.com/learn/atlas/memory-interface-choice/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Custom silicon ecosystem · Atlas v1.3.0

# Choosing SRAM, HBM, DDR, LPDDR or GDDR

Matches memory technology and package integration to a workload’s access pattern.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#memory-interface-choice)Register to storage hierarchy and product lifecycle

Learning objectiveCompare memory families using a workload and complete interface boundary.

## The mechanism

Memory alternatives solve different constraints. SRAM integrates near logic and supports fast local access, but has lower bit density than DRAM. HBM uses stacked DRAM and many short package connections. DDR commonly supplies expandable host memory; LPDDR emphasizes mobile-style power and signaling choices and also appears in some server and custom-accelerator designs. GDDR uses high-rate interfaces in discrete memory packages, providing another accelerator memory route. Capacity, sustained bandwidth, power, board area, package complexity and supply all matter. A valid comparison fixes a generation and configuration instead of treating one family as universally faster or cheaper.

1.  Determine which state must stay resident and which can be streamed without breaking the service target.
2.  Estimate reuse and concurrent accesses so the required bandwidth is tied to useful data movement.
3.  Evaluate local SRAM together with external DRAM rather than choosing one memory technology in isolation.
4.  Budget controller, PHY, package and board resources for the chosen width and signaling rate.
5.  Compare qualified configurations under the same workload while labeling price, supply and undocumented implementation details as unknown.

## Science and assumptions

### Raw interface rate

$$
B_{\mathrm{raw}}=\frac{wr}{8}
$$

Raw interface bandwidth is active pin count times effective bit rate per pin divided by eight.

Symbols and units

B\_raw

Raw directional interface byte rate

bytes/s

w

Active data-pin count

pins

r

Effective bit rate per active data pin

bits/(s·pin)

8

Bits per byte

bits/byte

w is active data pins and r is effective bits/s per pin; Braw is bytes/s. Multiply by a measured efficiency to estimate usable bandwidth.

Assumptions Do not double an already effective DDR data rate; command overhead, refresh and bank conflicts reduce realized throughput.

## Engineering example

Synthetic interfaces: 256 data pins at 16 Gbit/s and 1,024 pins at 4 Gbit/s both yield 512 GB/s raw. Their package requirements, power and latency can still be very different.

## Distinctions and tradeoffs

HBM is not simply DDR stacked higher, and high pin rate alone does not determine aggregate usable bandwidth.

HBM’s wide nearby interface adds advanced package dependencies; discrete DRAM choices move more routing onto a board, while additional SRAM competes with compute area.

The right memory balance differs for a small reusable recommendation working set, a large model’s weights and rapidly growing request KV state.

## Specifications and interfaces

Interface bandwidth

Data pins × bit rate / 8

Bytes/s before utilization losses; effective data rate already accounts for signaling transfers.

Technology choice

Memory device plus integration route

Controller/PHY, package, board and cooling must support the chosen interface.

### Interfaces

Workload memory demand Input

Resident bytes, reuse, burst size and access concurrency

Memory subsystem Output

Delivered data under capacity, power and integration constraints

## Check your understanding

### Which change can raise aggregate bandwidth without raising per-pin rate?

1.  Increasing the number of simultaneously active data pins
2.  Increasing only stored capacity
3.  Renaming memory as cache

Answer and reasoning

Increasing the number of simultaneously active data pins

A wider interface transfers more bits in parallel, provided controllers, channels and traffic can use that width.

## Evidence and scope

Pin counts and rates in the example are synthetic. No contemporary contract price, universal HBM advantage or interchangeable memory-controller compatibility is claimed.

Place read-only weights and mutable KV across specified tiers and inspect transfer paths; no HBF shipping-system benchmark or universal memory semantics are implied.

## Sources

-   [Graphics memory](https://www.micron.com/products/memory/graphics-memory)
-   [MTIA v1: Meta’s first-generation AI inference accelerator](https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/memory-interface-choice-7da0c849a214bfc9.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Full memory hierarchy and input path](https://semiaifoundry.com/learn/atlas/memory-hierarchy-route/)
-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)

### Related lessons

-   [DDR5 server memory](https://semiaifoundry.com/learn/atlas/ddr-memory/)
-   [Grace LPDDR5X memory](https://semiaifoundry.com/learn/atlas/lpddr-memory/)
-   [Custom inference silicon: Maia and MTIA](https://semiaifoundry.com/learn/atlas/inference-custom-silicon/)