{
  "schemaVersion": 1,
  "id": "atlas-lesson-mask-opc-layout",
  "title": "Masks, OPC and pattern-aware design",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Pre-distorts a mask so the process prints a desired wafer pattern.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/mask-opc-layout/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Fabrication / Repeated operations",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "The mask schematic omits proprietary correction algorithms and exact design rules. No vendor node is equated with a single printable dimension.",
  "contentCoverage": "published-lesson",
  "artifactUrl": "https://semiaifoundry.com/ai-atlas/lesson-data/mask-opc-layout-60eb587374a8eac3.json",
  "interactiveUrl": "https://semiaifoundry.com/ai-atlas/#mask-opc-layout",
  "related": [],
  "supersedes": [],
  "supersededBy": [],
  "contentHash": "24112ff4109503a458d2c6937ba20ccb30b92e468e880d252f76b325ef8bb3d9",
  "contentLength": 5379,
  "jsonUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-mask-opc-layout.json",
  "markdownUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-mask-opc-layout.md",
  "sections": [
    {
      "id": "section-1",
      "title": "Masks, OPC and pattern-aware design",
      "start": 50,
      "end": 392
    },
    {
      "id": "section-2",
      "title": "The mechanism",
      "start": 392,
      "end": 1557
    },
    {
      "id": "section-3",
      "title": "Science and assumptions",
      "start": 1557,
      "end": 1585
    },
    {
      "id": "section-4",
      "title": "Edge-error objective",
      "start": 1585,
      "end": 2414
    },
    {
      "id": "section-5",
      "title": "Engineering example",
      "start": 2414,
      "end": 2676
    },
    {
      "id": "section-6",
      "title": "Distinctions and tradeoffs",
      "start": 2676,
      "end": 3058
    },
    {
      "id": "section-7",
      "title": "Specifications and interfaces",
      "start": 3058,
      "end": 3311
    },
    {
      "id": "section-8",
      "title": "Interfaces",
      "start": 3311,
      "end": 3519
    },
    {
      "id": "section-9",
      "title": "Check your understanding",
      "start": 3519,
      "end": 3548
    },
    {
      "id": "section-10",
      "title": "Why test a corrected mask across focus and exposure conditions?",
      "start": 3548,
      "end": 3962
    },
    {
      "id": "section-11",
      "title": "Evidence and scope",
      "start": 3962,
      "end": 4301
    },
    {
      "id": "section-12",
      "title": "Sources",
      "start": 4301,
      "end": 4904
    },
    {
      "id": "section-13",
      "title": "Continue exploring",
      "start": 4904,
      "end": 4927
    },
    {
      "id": "section-14",
      "title": "Foundations",
      "start": 4927,
      "end": 5036
    },
    {
      "id": "section-15",
      "title": "Related lessons",
      "start": 5036,
      "end": 5379
    }
  ],
  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#mask-opc-layout"
    },
    {
      "title": "ASML — How microchips are made",
      "url": "https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made"
    },
    {
      "title": "KLA — Practical Applications of Measurement System Analysis",
      "url": "https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf"
    },
    {
      "title": "Applied Materials — New Ways to Shrink",
      "url": "https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/mask-opc-layout-60eb587374a8eac3.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "Lithography and pattern transfer",
      "url": "https://semiaifoundry.com/learn/atlas/lithography/"
    },
    {
      "title": "Coat, bake, expose and develop",
      "url": "https://semiaifoundry.com/learn/atlas/resist-track-development/"
    },
    {
      "title": "DUV, EUV and high-NA imaging",
      "url": "https://semiaifoundry.com/learn/atlas/lithography-resolution-focus/"
    },
    {
      "title": "Metrology, inspection and process windows",
      "url": "https://semiaifoundry.com/learn/atlas/fab-metrology-process-window/"
    }
  ],
  "recordHash": "5a4ddf4954c887cf3732d98507e372c2e559bddbfe817b02a42455e16ec7f209",
  "contentFormat": "text/markdown",
  "content": "Fabrication / Repeated operations · Atlas v1.3.0\n\n# Masks, OPC and pattern-aware design\n\nPre-distorts a mask so the process prints a desired wafer pattern.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#mask-opc-layout)Optical field to nanometer pattern; material states distinguished\n\nLearning objectiveExplain why manufacturable mask geometry differs from desired wafer geometry.\n\n## The mechanism\n\nA chip layout is not copied perfectly onto a wafer. Diffraction, neighboring shapes, resist response and etch transfer can move printed edges. Optical proximity correction modifies mask geometry to compensate for a calibrated imaging process. Some mask features assist printing without becoming intended device structures themselves. Mask manufacture and inspection introduce their own constraints, while multi-patterning can distribute one design across several exposures or spacer operations. The engineer therefore evaluates whether a design prints across a process window, not just at one ideal setting. This connects layout decisions and mask complexity directly to manufacturing yield.\n\n1.  Define the wafer target and distinguish it from the starting drawn mask geometry.\n2.  Calibrate an imaging model using relevant patterns and process conditions.\n3.  Modify mask edges or assist features to reduce predicted wafer-edge error.\n4.  Verify neighboring pattern contexts and off-nominal conditions rather than a single nominal image.\n5.  Manufacture, inspect and qualify the mask before interpreting wafer defects as scanner-only problems.\n\n## Science and assumptions\n\n### Edge-error objective\n\n$$\nE=\\sum_i w_i\\left(e_i^{\\mathrm{predicted}}-e_i^{\\mathrm{target}}\\right)^2\n$$\n\nThe illustrative edge-error objective sums each squared predicted-minus-target edge displacement weighted by that sample’s declared importance.\n\nSymbols and units\n\nE\n\nWeighted squared edge-placement error objective\n\nweighted nm²\n\nwᵢ\n\nDeclared relative importance of edge sample i\n\ndimensionless weight\n\neᵢ predicted\n\nPredicted position of edge sample i\n\nnm\n\neᵢ target\n\nTarget position for that edge sample\n\nnm\n\ni\n\nEdge/context sample index\n\ninteger index\n\nEdge coordinates e use length units; weights w state which edge/context matters. E has weighted length² units.\n\nAssumptions Illustrative optimization objective, not a proprietary OPC algorithm. Model error and manufacturing constraints require separate validation.\n\n## Engineering example\n\nIllustrative pair: an isolated line and a dense line array share the same drawn width but print different widths. Context-dependent correction can address the mismatch; a uniform global width change may improve one and worsen the other.\n\n## Distinctions and tradeoffs\n\nOPC does not mean every extra shape on a mask is an extra transistor on the wafer.\n\nMore detailed correction may expand the usable process window while increasing computation, mask complexity and verification effort.\n\nAccelerator layouts are valuable only if their dense patterns can be reliably fabricated and connected across many repeated layers.\n\n## Specifications and interfaces\n\nDesign object\n\nTarget wafer geometry vs mask geometry\n\nThese are different coordinate/material objects.\n\nError metric\n\nEdge placement error, length units\n\nSpecify target edge, process stage and measurement convention.\n\n### Interfaces\n\nLayout and calibrated model Input\n\nTarget features, process assumptions and design rules\n\nManufacturable mask set Output\n\nCorrected patterns with inspection and data-preparation requirements\n\n## Check your understanding\n\n### Why test a corrected mask across focus and exposure conditions?\n\n1.  A good nominal image can still have a narrow process window\n2.  Focus and dose never affect resist geometry\n3.  The mask is the finished wafer\n\nAnswer and reasoning\n\nA good nominal image can still have a narrow process window\n\nRobust printing requires tolerating realistic variation, not merely matching the target at one calibrated point.\n\n## Evidence and scope\n\nThe mask schematic omits proprietary correction algorithms and exact design rules. No vendor node is equated with a single printable dimension.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [ASML — How microchips are made](https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made)\n-   [KLA — Practical Applications of Measurement System Analysis](https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf)\n-   [Applied Materials — New Ways to Shrink](https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/mask-opc-layout-60eb587374a8eac3.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Lithography and pattern transfer](https://semiaifoundry.com/learn/atlas/lithography/)\n\n### Related lessons\n\n-   [Coat, bake, expose and develop](https://semiaifoundry.com/learn/atlas/resist-track-development/)\n-   [DUV, EUV and high-NA imaging](https://semiaifoundry.com/learn/atlas/lithography-resolution-focus/)\n-   [Metrology, inspection and process windows](https://semiaifoundry.com/learn/atlas/fab-metrology-process-window/)"
}