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  "title": "Grace LPDDR5X memory",
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  "description": "Provides the Grace CPU’s local main memory with short, energy-conscious package and board connections.",
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  "revisionDate": "2026-10-07",
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      "title": "Grace LPDDR5X memory",
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      "title": "Coherence does not remove path bottlenecks",
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      "title": "Check your understanding",
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      "title": "Why distinguish CPU LPDDR from GPU HBM in a coherent system?",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#lpddr-memory"
    },
    {
      "title": "NVIDIA: Grace CPU Superchip announcement",
      "url": "https://nvidianews.nvidia.com/news/nvidia-introduces-grace-cpu-superchip"
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    {
      "title": "NVIDIA GB200 NVL72 specifications",
      "url": "https://www.nvidia.com/en-us/data-center/gb200-nvl72/"
    },
    {
      "title": "NVIDIA: Inside Grace CPU architecture",
      "url": "https://developer.nvidia.com/blog/inside-nvidia-grace-cpu-nvidia-amps-up-superchip-engineering-for-hpc-and-ai/"
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      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "DDR5 server memory",
      "url": "https://semiaifoundry.com/learn/atlas/ddr-memory/"
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    {
      "title": "High-bandwidth memory stack",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack/"
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    {
      "title": "Host CPU",
      "url": "https://semiaifoundry.com/learn/atlas/host-cpu/"
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      "title": "Grace Blackwell Superchip",
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  "content": "Host platform · Atlas v1.3.0\n\n# Grace LPDDR5X memory\n\nProvides the Grace CPU’s local main memory with short, energy-conscious package and board connections.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#lpddr-memory)Memory packages near the Grace CPU; exact module layout varies\n\nLearning objectiveIdentify the limiting bandwidth along a remote CPU-memory path instead of treating coherent capacity as local HBM.\n\n## The mechanism\n\nLPDDR5X is dynamic memory designed with strong attention to power efficiency. Grace uses it for CPU main memory, giving the host processor a local store distinct from the GPU’s HBM. Coherent CPU–GPU connectivity can simplify access to a shared address space, but it does not erase the physical difference between these memories or their paths. CPU memory and HBM are distinct reservoirs connected by an interconnect, so remote access still incurs data movement and path costs. Capacity options and rated bandwidth vary by module configuration. An early architecture estimate and a later product capacity describe different disclosures unless their configuration and conditions are explicitly reconciled. The useful question is which memory contains each part of the workload and how often that part must travel.\n\n1.  Grace keeps CPU-resident program and data state in its local LPDDR5X memory subsystem.\n2.  The CPU reads and updates that state through its memory controllers.\n3.  When GPU work needs data located there, the coherent interconnect provides a path while preserving the distinction between physical memory locations.\n\n## Science and assumptions\n\n### Coherence does not remove path bottlenecks\n\n$$\nB_{\\mathrm{remote}}\\le\\min(B_{\\mathrm{source\\ memory}},B_{\\mathrm{interconnect}},B_{\\mathrm{destination}})\n$$\n\nRemote-access bandwidth cannot exceed the smallest effective bandwidth of the source memory, interconnect and destination.\n\nSymbols and units\n\nB\\_remote\n\nSustained remote-access payload rate\n\nbytes/s\n\nB\\_source memory\n\nEffective source-memory rate in the selected direction\n\nbytes/s\n\nB\\_interconnect\n\nEffective intervening-link rate in that direction\n\nbytes/s\n\nB\\_destination\n\nEffective receiving-boundary rate\n\nbytes/s\n\nEach B is effective payload bandwidth at the relevant one-direction path boundary. Reading CPU-resident data from a GPU must traverse both the CPU memory subsystem and the interconnect, even when a coherent address space makes that access convenient. Capacity can be shared logically without turning every memory location into an equally fast physical resource.\n\nAssumptions A serial-path upper bound for sustained transfers with adequate concurrency. Cache hits, compression, competing traffic, routing, and write/read direction change the applicable boundaries; do not substitute a summed bidirectional rating for one-way payload bandwidth.\n\n## Engineering example\n\nSynthetic one-way path: effective source memory, link and destination limits of 300, 200 and 500 GB/s give a ceiling of min(300, 200, 500) = 200 GB/s. Moving 20 GB therefore takes at least 0.1 s before access startup or contention. Raising only destination bandwidth cannot improve that bound.\n\n## Distinctions and tradeoffs\n\nA coherent address space does not merge CPU LPDDR and GPU HBM into one memory with identical performance. The physical route to each location still matters.\n\nCloser memory integration can improve energy efficiency but offers different expansion and service options than socketed DIMMs. Coherent access is convenient, yet locality still affects performance.\n\nHost memory supports preparation, orchestration, and data that do not reside permanently in HBM. Efficient placement avoids turning the CPU–GPU link into an unnecessary bottleneck.\n\n## Specifications and interfaces\n\nGB200 CPU memory\n\nUp to 480 GB LPDDR5X\n\nPer Grace Blackwell Superchip product table; configurations vary.\n\nPublished bandwidth\n\nUp to 512 GB/s\n\nProduct maximum; do not assume every capacity option achieves it.\n\nStorage role\n\nCPU main memory\n\nDistinct from GPU HBM3E despite coherent access support.\n\n### Interfaces\n\nGrace requests Input\n\nCPU reads, writes, and memory management\n\nCPU data Output\n\nHost working-set values\n\nCoherent GPU access Output\n\nData crossing the CPU–GPU link when requested\n\n## Check your understanding\n\n### Why distinguish CPU LPDDR from GPU HBM in a coherent system?\n\n1.  Coherence means no bits ever move between components.\n2.  They are the same physical memory chips under two names.\n3.  They have different capacities, bandwidths, and access paths.\n\nAnswer and reasoning\n\nThey have different capacities, bandwidths, and access paths.\n\nCoherence simplifies some programming tasks, but good placement still avoids unnecessary transfers between physically different memory systems.\n\n## Historical context\n\n### 2022 · Grace CPU Superchip announces server LPDDR5X integration\n\nThe March 2022 Grace CPU Superchip announcement described an LPDDR5X memory subsystem with error correction in a data-center CPU platform. This is a Grace platform milestone, not the invention of LPDDR memory.\n\n[NVIDIA: Grace CPU Superchip announcement](https://nvidianews.nvidia.com/news/nvidia-introduces-grace-cpu-superchip)\n\n## Evidence and scope\n\nThese rates are synthetic, not Grace specifications. The linked architecture documents establish distinct CPU memory and HBM paths; payload direction, configuration, cache effects and attained bandwidth must be specified.\n\nPlace read-only weights and mutable KV across specified tiers and inspect transfer paths; no HBF shipping-system benchmark or universal memory semantics are implied.\n\n## Sources\n\n-   [NVIDIA GB200 NVL72 specifications](https://www.nvidia.com/en-us/data-center/gb200-nvl72/)\n-   [NVIDIA: Inside Grace CPU architecture](https://developer.nvidia.com/blog/inside-nvidia-grace-cpu-nvidia-amps-up-superchip-engineering-for-hpc-and-ai/)\n-   [NVIDIA: Grace CPU Superchip announcement](https://nvidianews.nvidia.com/news/nvidia-introduces-grace-cpu-superchip)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/lpddr-memory-478a539325968c92.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [DDR5 server memory](https://semiaifoundry.com/learn/atlas/ddr-memory/)\n-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)\n\n### Related lessons\n\n-   [Host CPU](https://semiaifoundry.com/learn/atlas/host-cpu/)\n-   [Grace Blackwell Superchip](https://semiaifoundry.com/learn/atlas/grace-blackwell-superchip/)"
}