# Loaded CMOS transfer, noise and transition delay

Canonical: https://semiaifoundry.com/learn/atlas/loaded-inverter-transition/
Revision: 2026-10-07
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Devices and logic · Atlas v1.3.0

# Loaded CMOS transfer, noise and transition delay

Compare the same cell’s DC voltage-transfer contract with its explicitly loaded charging and discharging behavior.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#loaded-inverter-transition)Declared 2 μm channel, nanometre oxide inputs and one lumped circuit; schematic geometry

Learning objectiveCompute loaded delay and conservative DC noise margins, recognize the ideal model’s vertical transition, and distinguish load-induced timing failure from electrical asymmetry.

## The mechanism

A CMOS inverter’s static transfer describes the output voltage after currents balance. Its transient response also depends on the charge that must move into or out of its load. These are related but distinct tests of a useful logic cell. The specimen solves the long-channel triode and saturation branches directly and locates the two unity-gain points that define its static noise margins. Because channel-length modulation is deliberately zero, the exact switching input admits an interval of balanced outputs; the graph shows that model boundary rather than fabricating a unique voltage. Loaded transitions use a separate rail-to-rail input-step experiment and integrate the same current law against a constant capacitance. Fanout therefore changes delay without moving the DC transfer. A weakened nMOS can instead shift the switching input, make the noise margins unequal and slow only one direction. These cases show why a library cell needs a declared load, input convention and numerical model before its timing can be meaningfully discussed.

1.  The nMOS and pMOS current magnitudes use source-referenced voltages and positive threshold magnitudes.
2.  The DC operating point balances pull-up and pull-down current within each valid long-channel regime.
3.  The exact λ=0 transition remains set-valued; the model exposes its output interval and does not report a finite gain there.
4.  The two separate slope-minus-one points define actual VOL, VOH, VIL and VIH for the static noise calculation.
5.  Each ideal input step leaves one transistor charging or discharging the constant output load; the piecewise current is integrated to stated voltage thresholds.
6.  Increasing fanout, changing electrical asymmetry or changing acceptance limits reveals different failure causes without equating static logic with timing.

## Science and assumptions

### Piecewise long-channel current magnitude

$$
I(\beta,V_T,V_G,V_D)=\begin{cases}0,&V_G\leq V_T,\\\beta[(V_G-V_T)V_D-V_D^2/2],&0\leq V_D<V_G-V_T,\\\beta(V_G-V_T)^2/2,&V_D\geq V_G-V_T.\end{cases}
$$

Current is zero below threshold, follows the triode expression below the overdrive drain voltage, and saturates at the square-law magnitude.

Symbols and units

I

Drain-current magnitude

A

β

Current factor

A/V²

VT,VG,VD

Positive threshold magnitude and source-referenced gate/drain voltage magnitudes

V

DC transfer balances the two currents. pMOS uses VSG, VSD and |VTp| in the same positive-magnitude function. The exact λ=0 switching input admits an interval of output voltages.

Assumptions Long-channel, strong-inversion, constant mobility, no channel-length modulation, leakage, body-bias changes or short-channel effects. Ideal cutoff is not real subthreshold behavior.

### One output load connects to the following gates

$$
C_L=f\,C_{\mathrm{ox}}(W_n+W_p)L+C_{\mathrm{extra}}
$$

Total load is fanout times the selected next-gate oxide-area capacitance plus an explicitly supplied extra load.

Symbols and units

CL

Total constant output load

F

f

Number of identical following inverters

count

Cox

Oxide capacitance per area

F/m²

Wn,Wp,L

Following gate geometry

m

Cextra

Supplied extra lumped capacitance

F

The geometry used for the next inverter matches the specimen. Increasing fanout raises a positive constant capacitance without altering the DC current-balance curve.

Assumptions Constant full oxide-area approximation, not voltage-dependent gate capacitance. The extra load is supplied, not an extracted wire/junction model; intrinsic and overlap parasitics are omitted.

### Loaded delay from the current integral

$$
t_{PHL}=C_L\int_{V_{DD}/2}^{V_{DD}}\frac{dv}{I_n(V_{DD},v)},\qquad t_{PLH}=C_L\int_{V_{DD}/2}^{V_{DD}}\frac{dv}{|I_p(V_{DD},v)|}
$$

The 50% step delays integrate the constant load divided by the conducting transistor’s voltage-dependent current.

Symbols and units

tPHL,tPLH

Output high-to-low and low-to-high 50% delays

s

CL

Constant output load

F

v,VDD

Drain-voltage magnitude integration variable and supply

V

In,|Ip|

Modeled nMOS and pMOS current magnitudes

A

The implementation evaluates saturation and triode portions analytically. Independent numerical quadrature checks the integral, improving on a constant-current hand estimate within this same ideal model.

Assumptions Instantaneous rail-to-rail input step, one conducting pull device, constant load and ideal initial rail. These are mathematical model times, not measured silicon delays. The output approaches its final rail asymptotically.

### Use the actual unity-gain output levels

$$
\left.\frac{dV_{out}}{dV_{in}}\right|_{V_{IL},V_{IH}}=-1,\qquad NM_L=V_{IL}-V_{OL},\quad NM_H=V_{OH}-V_{IH}
$$

The two unity-gain inputs define corresponding output levels; low and high DC margins are their cross-stage differences.

Symbols and units

VIL,VIH

Low and high unity-gain input voltages

V

VOL,VOH

Corresponding low and high output voltages

V

NML,NMH

Low and high static noise margins

V

VOL is Vout(VIH) and VOH is Vout(VIL). The model uses those actual curve levels instead of substituting ideal zero and supply rails.

Assumptions Static cascade convention for identical gates in the declared model; no noise spectrum, transient susceptibility, error rate or statistical distribution is predicted.

## Engineering example

With default INV-01, VIL=0.5364598 V, VIH=0.6635402 V, VOL=0.0635402 V and VOH=1.1364598 V. Both noise margins are 0.4729196 V; the 50% step delay is 0.6997759 ns in each direction. Four following loads increase total capacitance to 230.99584 fF and delay to 2.4773623 ns, while all four static voltages and noise margins remain unchanged. The 1 ns timing gate fails. Reducing nMOS mobility to 0.5× and adding 120 mV to its threshold instead produces a 1.8745095 ns falling delay and 0.3967162 V high noise margin, failing the chosen 0.4 V noise requirement as well.

## Distinctions and tradeoffs

Correct static output and positive noise margins do not prove a specified loaded transition deadline.

Geometry, current, capacitance and noise can move together or in opposite directions. The model exposes that coupling while keeping its deliberately ideal physics and chosen acceptance contract explicit.

Every accelerator is assembled from physical devices whose behavior must satisfy cell-level requirements before higher-level arithmetic and system performance claims are meaningful.

## Specifications and interfaces

Specimen

INV-01

Same evaluated material/electrical state through all views.

Geometry

L=2 μm; Wn=2 μm; Wp=6 μm

Declared planar long-channel dimensions; not a process-node label.

Supply

1.2 V

Fixed teaching input; no commercial operating point is implied.

### Interfaces

Material and process scenario Input

Nominal/evaluated oxide, declared nMOS mobility/threshold perturbation and load

Cell acceptance evidence Output

Current, transfer, noise, delay and independent pass/fail gates

## Check your understanding

### Fanout rises from one to four identical loads while device parameters stay fixed. Which result changes in this model?

1.  Only the switching threshold
2.  The loaded delay changes; the DC transfer is unchanged
3.  Neither delay nor DC transfer changes

Answer and reasoning

The loaded delay changes; the DC transfer is unchanged

The positive load multiplies transient charging time. It does not enter the static current-balance equation.

## Evidence and scope

The physical equations and conventions are primary-source informed. The parameter values, corners, constraints and results are authored teaching choices; no commercial process or human specialist review is represented.

The process-cell-acceptance-1 studio carries INV-01 through this exact mathematical specimen. It does not run fabrication, TCAD, a SPICE executable or a foundry model.

## Sources

-   [MIT 6.012 Fall 2005 — Lecture 9](https://ocw.mit.edu/courses/6-012-microelectronic-devices-and-circuits-fall-2005/5c5960f14ae37d0a65478c4f3f628d98_lec9.pdf)
-   [MIT 6.012 Fall 2005 — Lecture 10](https://ocw.mit.edu/courses/6-012-microelectronic-devices-and-circuits-fall-2005/0498bbf0f0e585507d9cfe5dc3bd54b1_lec10.pdf)
-   [MIT 6.012 Fall 2005 — Lecture 12](https://www.ocw.mit.edu/courses/6-012-microelectronic-devices-and-circuits-fall-2005/74c08e0cdcdab837d4eaceaf2384d646_lec12.pdf)
-   [MIT 6.012 Fall 2005 — Lecture 14](https://www.ocw.mit.edu/courses/6-012-microelectronic-devices-and-circuits-fall-2005/6bec6dd1b07b02a1a84098b78f068cc3_lec14.pdf)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/loaded-inverter-transition-937b321ffb29b496.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Oxide variation to electrical cell acceptance](https://semiaifoundry.com/learn/atlas/oxide-to-cell-acceptance/)
-   [Complementary CMOS inverter](https://semiaifoundry.com/learn/atlas/inverter/)

### Related lessons

-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)
-   [Clock tree and gated timing domains](https://semiaifoundry.com/learn/atlas/clock/)
-   [Metal gate and high-k dielectric](https://semiaifoundry.com/learn/atlas/gate-stack/)