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      "title": "Lithography and pattern transfer",
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      "title": "What does lithographic exposure directly create?",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#lithography"
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    {
      "title": "ASML — Making EUV: From Lab to Fab",
      "url": "https://www.asml.com/en/company/stories/2022/making-euv-lab-to-fab"
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    {
      "title": "ASML — Light and Lasers",
      "url": "https://www.asml.com/en/technology/lithography-principles/light-and-lasers"
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    {
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      "title": "Wafer and fabrication hierarchy",
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      "title": "Metal–oxide–semiconductor field-effect transistor",
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      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
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      "url": "https://semiaifoundry.com/learn/atlas/cmp/"
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  "content": "Fabrication · Atlas v1.3.0\n\n# Lithography and pattern transfer\n\nTurns a circuit pattern into spatially selected regions on a wafer.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#lithography)Optical pattern transfer to nanometer-scale features\n\nLearning objectiveUse the Rayleigh relation as a resolution scaling argument.\n\n## The mechanism\n\nLithography projects a patterned exposure onto a light-sensitive resist on the wafer. The developed resist then helps select where later processing changes the material; exposure alone does not deposit a complete transistor. Repeating aligned patterning steps lets many different device and wiring features meet in the intended places. Modern chipmaking uses different exposure technologies for different layers, so EUV is part of a larger manufacturing flow. Wavelength is one factor in resolution alongside optics and process methods. The atlas separates the pattern, resist, and underlying structure to show how a design acquires physical location before material processing turns that location into a functional feature.\n\n1.  Encode the desired spatial pattern on the lithographic mask and exposure system.\n2.  Expose and develop resist so selected regions can guide later material processing.\n3.  Align and repeat the process for additional features and layers in the circuit.\n\n## Science and assumptions\n\n### Rayleigh resolution relation\n\n$$\n\\mathrm{CD}=k_1\\frac{\\lambda}{\\mathrm{NA}}\n$$\n\nCritical dimension equals the process factor times exposure wavelength divided by numerical aperture.\n\nSymbols and units\n\nCD\n\nCritical dimension in the selected resolution definition\n\nnm\n\nk₁\n\nProcess-dependent imaging factor\n\ndimensionless\n\nλ\n\nExposure wavelength\n\nnm\n\nNA\n\nNumerical aperture\n\ndimensionless\n\nCritical dimension depends on exposure wavelength, numerical aperture, and a process-dependent imaging factor. This explains why wavelength, optics, and patterning methods must advance together.\n\nAssumptions Lithographic scaling relation, not a direct equation for transistor gate length or a foundry node name; k₁ summarizes process and imaging choices.\n\n## Engineering example\n\nHolding k₁ and wavelength fixed while increasing NA lowers the nominal CD, but reduces the depth-of-focus estimate quadratically.\n\n## Distinctions and tradeoffs\n\nEUV’s 13.5 nm wavelength is not a measurement of a transistor gate or an entire process-node feature.\n\nFiner patterning enables denser structures. Optical complexity and process control raise manufacturing demands.\n\nLithography reproduces the enormous circuit patterns needed for accelerators. Accuracy lets tiny device features connect as designed.\n\n## Specifications and interfaces\n\nEUV wavelength\n\n13.5 nm\n\nExposure wavelength; not transistor gate length.\n\nDUV example\n\n193 nm\n\nArF exposure technology remains part of chip manufacturing.\n\nCritical relationship\n\nLayer alignment\n\nFeatures must register across repeated patterning steps.\n\n### Interfaces\n\nMask pattern and light Input\n\nSpatial exposure information\n\nPatterned resist Output\n\nSelective template for subsequent processing\n\n## Check your understanding\n\n### What does lithographic exposure directly create?\n\n1.  A complete working GPU\n2.  A spatial exposure pattern in resist\n3.  Every metal layer simultaneously\n\nAnswer and reasoning\n\nA spatial exposure pattern in resist\n\nExposure is one stage of pattern transfer. Subsequent material-processing steps create the actual device or wiring feature.\n\n## Historical context\n\n### 2010 · Pre-production NXE:3100 EUV system ships\n\nThe pre-production system moved 13.5 nm lithography closer to manufacturing integration. It preceded later production platforms and should not be mistaken for immediate universal EUV adoption.\n\n[ASML — Making EUV: From Lab to Fab](https://www.asml.com/en/company/stories/2022/making-euv-lab-to-fab)\n\n### 2013 · First NXE:3300 production EUV system ships\n\nASML’s production-system shipment marked another step in the long progression from experimental exposure to manufacturing use.\n\n[ASML — Making EUV: From Lab to Fab](https://www.asml.com/en/company/stories/2022/making-euv-lab-to-fab)\n\n## Evidence and scope\n\nThe variables are illustrative; stochastic variation, overlay and a qualified process window are separate.\n\nVary wavelength and aperture in the Rayleigh resolution/focus model; stochastic defects and qualified tool configurations are not predicted.\n\n## Sources\n\n-   [ASML — Light and Lasers](https://www.asml.com/en/technology/lithography-principles/light-and-lasers)\n-   [ASML — Rayleigh Criterion](https://www.asml.com/en/technology/lithography-principles/rayleigh-criterion)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/lithography-cc3bc7e0fe2c8194.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Wafer and fabrication hierarchy](https://semiaifoundry.com/learn/atlas/silicon-wafer/)\n\n### Related lessons\n\n-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n-   [Chemical mechanical planarization](https://semiaifoundry.com/learn/atlas/cmp/)\n-   [Metal gate and high-k dielectric](https://semiaifoundry.com/learn/atlas/gate-stack/)"
}