# DFT, probe, binning and known-good die

Canonical: https://semiaifoundry.com/learn/atlas/known-good-die-test/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Fabrication / Control, test and ramp · Atlas v1.3.0

# DFT, probe, binning and known-good die

Uses designed test access and measurements to screen material before costly assembly.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#known-good-die-test)Feature measurements, wafer maps and time-dependent production

Learning objectiveExplain what DFT, probe, repair and binning establish before package integration.

## The mechanism

Testing needs access to behavior that ordinary product pins may not expose. Scan structures improve controllability and observability of logic; built-in self-test can exercise embedded memories; parametric structures measure electrical process behavior. Wafer probing then contacts designated pads to apply tests before singulation. Redundant memory resources may repair eligible faults, and binning classifies parts by defined function or performance. A known-good die has passed a stated screening flow; it is not guaranteed free of every latent defect. This matters especially when a package combines several valuable dies that can be lost together during subsequent integration.

1.  Build test access into the design so internal states can be controlled or observed.
2.  Measure process parameters separately from structural and application-oriented functional behavior.
3.  Probe dies under a defined program and retain failing-site and condition information.
4.  Apply permitted redundancy and classify function/performance bins using explicit product criteria.
5.  Preserve map identity through dicing and test again at later integration stages when new failure mechanisms appear.

## Science and assumptions

### Screened defect probability

$$
\Pr(\mathrm{defect}\mid\mathrm{pass})=\frac{p(1-c)}{1-pc}
$$

Residual defect probability after a pass is incoming defect probability times the missed-detection fraction, divided by total pass probability.

Requires pass probability 1 − pc > 0. It assumes no false rejection of defect-free dies and one defined defect population.

Symbols and units

Pr(defect given pass)

Residual defect probability among passing dies

probability

p

Incoming probability of the defined defect

probability

c

Detection probability conditional on that defect

probability

p is incoming defect probability and c detection probability for that defect population; all terms are dimensionless.

Assumptions Assumes no false rejects and a single defined defect population. Real fault coverage and test sensitivity are not interchangeable without validation.

## Engineering example

Synthetic screening: p = 0.10 and c = 0.90 leave 0.01/0.91 ≈ 1.10% defective among passing parts under the simple assumptions. Applying the raw 10% defect rate again to screened parts would double-count the screen.

## Distinctions and tradeoffs

Known-good die means passed a defined test set; it does not mean perfect detection of all current and future faults.

More test coverage can reduce expensive assembly escapes while adding test time, design overhead and possible over-screening.

Good-die selection protects packages containing compute, interposers and multiple memory stacks from avoidable incoming-part losses.

## Specifications and interfaces

Test boundary

Parametric, structural and functional tests

Different tests cover different fault models and operating conditions.

Output state

Passed specified tests / repaired / binned

Known-good status must include the test revision and conditions.

### Interfaces

Wafer and test access Input

DFT structures, probe pads and defined test program

Screened die map Output

Bin, repair status and genealogy for singulation and assembly

## Check your understanding

### Why is final package testing still needed after incoming dies passed wafer probe?

1.  Wafer probe has no useful information
2.  Every tested die becomes electrically identical
3.  Assembly can introduce new interconnect or mechanical failures

Answer and reasoning

Assembly can introduce new interconnect or mechanical failures

Incoming screening and assembly verification examine different failure opportunities and interfaces.

## Evidence and scope

No actual tester coverage or product escape rate is asserted. Dicing routes vary, and not all damage can be detected by the same test.

No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.

## Sources

-   [Advantest — Semiconductor test glossary](https://www.advantest.com/en/investors/ir-library/glossary/)
-   [Intel Foundry — Accelerating HPC and AI](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/known-good-die-test-0f15708098fcc7e5.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Wafer maps and good-die yield](https://semiaifoundry.com/learn/atlas/yield-wafer-defect-model/)

### Related lessons

-   [Edge-triggered D flip-flop](https://semiaifoundry.com/learn/atlas/flipflop/)
-   [Six-transistor static memory cell](https://semiaifoundry.com/learn/atlas/sram/)
-   [Wafer handling, carriers and genealogy](https://semiaifoundry.com/learn/atlas/wafer-handling-genealogy/)
-   [HBM stack assembly, repair and staged test](https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/)