# Complementary CMOS inverter

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Revision: 2026-10-07
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Digital circuits · Atlas v1.3.0

# Complementary CMOS inverter

Turns one binary voltage state into its complement.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#inverter)Microscopic cell containing two complementary devices

Learning objectivePredict the output state and estimate the dynamic switching power of a loaded CMOS inverter.

## The mechanism

A CMOS inverter joins a p-channel pull-up device to an n-channel pull-down device. Both gates receive the input; their shared output connects toward the supply for one input state and toward ground for the other. This complementary relationship restores useful signal levels and lets gates drive later gates. During a transition, the output load must charge or discharge, and the device currents change continuously. Static CMOS therefore has low ideal steady-state conduction but not zero real power consumption. The atlas exposes the two devices and the output capacitance instead of showing only a triangular symbol. This is the first place where the physical transistor becomes an explicit logical operation.

1.  Apply the same input voltage to a complementary pMOS/nMOS pair.
2.  Connect the output toward the supply or ground through the appropriate conducting device.
3.  Charge or discharge the output load so it enters the opposite valid logic range.

## Science and assumptions

### Switching power

$$
P_{\mathrm{dynamic}}\approx\alpha C_{\mathrm{load}}V_{DD}^2 f
$$

Dynamic power is approximately charging activity times load capacitance times supply voltage squared times clock frequency.

Symbols and units

P\_dynamic

Dynamic switching power

W

α

Effective charging events per clock period

events/cycle

C\_load

Switched load capacitance

F

V\_DD

Supply voltage

V

f

Clock frequency

cycles/s

A switching node repeatedly charges and discharges its load. Voltage has a squared influence in this model, linking device-level supply choices to chip-level power.

Assumptions α counts effective charging activity per clock period; model excludes leakage and short-circuit power and assumes a lumped load.

## Engineering example

Synthetic node: with charging activity α = 0.25 per cycle, C = 10 fF, V = 1 V and f = 1 GHz, αCV²f = 2.5 μW. Raising V to 1.2 V gives 3.6 μW, a 44% increase before leakage and short-circuit power.

## Distinctions and tradeoffs

Low ideal steady-state CMOS power does not mean zero power: switching, leakage, and transition currents remain.

Upsizing can drive larger loads faster. It also increases input capacitance and area.

Inverters restore and transform signals throughout a processor. They appear inside memory and more complex logic networks.

## Specifications and interfaces

Logic equation

Y = NOT A

One binary input, one binary output.

Basic implementation

2 transistors

One pMOS and one nMOS in the canonical inverter.

Physical output

Voltage range

Logic values rely on valid electrical levels.

### Interfaces

A Input

Binary-encoded input voltage

Y Output

Complementary output voltage

## Check your understanding

### What does an inverter do to a valid logic input?

1.  Counts how many electrons are in the wafer
2.  Returns the same value permanently
3.  Produces its logical complement

Answer and reasoning

Produces its logical complement

The complementary transistor pair maps a low input toward a high output and a high input toward a low output.

## Historical context

### 1963 · Wanlass files complementary field-effect circuitry

Complementary n- and p-channel switching provided a path to low standby-power logic. The patent was filed in 1963 and granted in 1967.

[Wanlass — US3356858A](https://patents.google.com/patent/US3356858A/en)

## Evidence and scope

The switching model and complementary topology follow the linked CMOS lecture. Values are synthetic; valid logic levels, transfer gain and noise margins require a device and load model.

Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.

## Sources

-   [MIT 6.012 — CMOS Inverter Transfer Characteristics](https://ocw.mit.edu/courses/6-012-microelectronic-devices-and-circuits-fall-2005/b5c8c475943132703a6dd50c479f9714_lec13.pdf)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/inverter-ceec9a037236becd.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)

### Related lessons

-   [Two-input CMOS NAND gate](https://semiaifoundry.com/learn/atlas/nand/)
-   [Six-transistor static memory cell](https://semiaifoundry.com/learn/atlas/sram/)
-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)