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  "title": "Interposer and redistribution layers",
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  "revisionDate": "2026-10-07",
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  "topic": "Advanced packaging",
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      "title": "Interposer and redistribution layers",
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      "title": "The mechanism",
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      "title": "Long resistive routes can become disproportionately slow",
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      "title": "Continue exploring",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#interposer"
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    {
      "title": "TSMC: CoWoS platform history and technology",
      "url": "https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm"
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    {
      "title": "TSMC research: High Performance, High Density RDL",
      "url": "https://research.tsmc.com/page/off-chip-interconnect/19.html"
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    {
      "title": "MIT: Communication System Design, interconnect and wire scaling",
      "url": "https://ocw.mit.edu/courses/6-973-communication-system-design-spring-2006/44d1cff68d0f994cca25442de3e1ac78_lecture_5.pdf"
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    {
      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
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    {
      "title": "Through-silicon via",
      "url": "https://semiaifoundry.com/learn/atlas/through-silicon-via/"
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    {
      "title": "GPU logic dies",
      "url": "https://semiaifoundry.com/learn/atlas/gpu-die/"
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    {
      "title": "High-bandwidth memory stack",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack/"
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    {
      "title": "Microbumps and bonding joints",
      "url": "https://semiaifoundry.com/learn/atlas/microbump/"
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    {
      "title": "Package substrate",
      "url": "https://semiaifoundry.com/learn/atlas/package-substrate/"
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  "content": "Advanced packaging · Atlas v1.3.0\n\n# Interposer and redistribution layers\n\nConnects logic dies and memory through dense package-level wiring.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#interposer)Millimeter-to-centimeter interposer with micrometer-scale routing\n\nLearning objectiveExplain why longer package wiring has an RC cost.\n\n## The mechanism\n\nThe interposer is the wiring platform between fine-pitch die connections and the larger package substrate. It lets a GPU sit close to several memory stacks with many parallel connections. Advanced packaging does not always use a single uniform slab of silicon: TSMC’s CoWoS family includes silicon interposers, redistribution-layer approaches, and local silicon interconnects embedded where higher connection density is needed. A GPU-to-HBM route passes through selected conductors and connections in the routing platform. A generic routing construction does not establish the exact unpublished package cross-section of a named accelerator. Dense local wiring makes the package function like a small system assembled from dies optimized for different jobs.\n\n1.  Fine-pitch terminals from logic and memory land on the dense interconnect platform.\n2.  Patterned routing layers carry many short lateral connections between neighboring dies and memory stacks.\n3.  Other routes transition toward the package substrate, which connects the integrated assembly to its wider system.\n\n## Science and assumptions\n\n### Long resistive routes can become disproportionately slow\n\n$$\nt_{\\mathrm{delay}}\\propto R^{\\prime}C^{\\prime}\\ell^2\n$$\n\nDistributed-RC route delay scales with resistance per length times capacitance per length times route length squared.\n\nSymbols and units\n\nt\\_delay\n\nCharacteristic unbuffered route delay\n\ns\n\nR′\n\nResistance per route length\n\nΩ/m\n\nC′\n\nCapacitance per route length\n\nF/m\n\nℓ\n\nRoute length\n\nm\n\nR′ and C′ are resistance and capacitance per unit length; ℓ is route length. In a distributed RC approximation, doubling a comparable unbuffered route can increase its delay by about four times. Dense package integration shortens routes between logic and memory and can reduce capacitance as well as physical distance, helping explain its performance and energy value.\n\nAssumptions RC-dominated, uniform unbuffered interconnect with fixed cross-section and loading convention. High-speed package channels can require transmission-line and full electromagnetic models; the proportionality is not a measured interposer delay specification.\n\n## Engineering example\n\nIf both distributed R′ and C′ stay constant, doubling the route length increases the simple delay proportional to length squared.\n\n## Distinctions and tradeoffs\n\nNot every interposer is one uniform silicon sheet. CoWoS variants can use silicon, redistribution layers, and local silicon interconnects in different constructions.\n\nDenser routing reduces connection distance but increases fabrication and assembly complexity. Different interposer styles balance routing density, mechanical behavior, package size, and cost.\n\nThe memory bandwidth of an accelerator depends on the wiring that joins logic and HBM. Advanced packaging enables system-level gains even when transistor scaling alone slows.\n\n## Specifications and interfaces\n\nIntegration class\n\n2.5D heterogeneous packaging\n\nLogic and memory sit side by side on dense interconnect structures.\n\nCoWoS-L structure\n\nRDL plus local silicon interconnects\n\nTSMC platform description, not a specific Blackwell bill of materials.\n\nCoWoS-S example\n\nUp to about 2,700 mm² interposer\n\nTSMC stated 3.3-reticle platform capability; not a GPU die area.\n\n### Interfaces\n\nDie terminals Input\n\nFine-pitch signals from GPU and HBM\n\nLateral links Output\n\nDense routes between adjacent dies\n\nSubstrate escape Output\n\nSignals and power paths toward the package substrate\n\n## Check your understanding\n\n### What is the interposer’s central contribution to an AI accelerator?\n\n1.  It executes the operating system.\n2.  It provides dense local routing between logic dies and memory.\n3.  It replaces all cooling equipment.\n\nAnswer and reasoning\n\nIt provides dense local routing between logic dies and memory.\n\nHigh-bandwidth memory needs a large number of nearby connections to the processor. Dense package routing makes those connections physically practical.\n\n## Historical context\n\n### 2012 · TSMC CoWoS enters volume production\n\nTSMC dates CoWoS volume production to 2012. The packaging platform evolved to integrate multiple logic dies and high-bandwidth memory through dense local interconnect, making the package an important part of system architecture.\n\n[TSMC: CoWoS platform history and technology](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm)\n\n## Evidence and scope\n\nThe relation is a distributed-line intuition, not a package timing signoff.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [TSMC CoWoS advanced packaging](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm)\n-   [TSMC research: High Performance, High Density RDL](https://research.tsmc.com/page/off-chip-interconnect/19.html)\n-   [MIT: Communication System Design, interconnect and wire scaling](https://ocw.mit.edu/courses/6-973-communication-system-design-spring-2006/44d1cff68d0f994cca25442de3e1ac78_lecture_5.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/interposer-5811de9d3ee1ec1d.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n-   [Through-silicon via](https://semiaifoundry.com/learn/atlas/through-silicon-via/)\n\n### Related lessons\n\n-   [GPU logic dies](https://semiaifoundry.com/learn/atlas/gpu-die/)\n-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)\n-   [Microbumps and bonding joints](https://semiaifoundry.com/learn/atlas/microbump/)\n-   [Package substrate](https://semiaifoundry.com/learn/atlas/package-substrate/)\n-   [Chemical mechanical planarization](https://semiaifoundry.com/learn/atlas/cmp/)"
}