# Signal integrity, timing and the eye diagram

Canonical: https://semiaifoundry.com/learn/atlas/interface-signal-eye/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Chip-to-hall integration · Atlas v1.3.0

# Signal integrity, timing and the eye diagram

Tests whether a receiver can distinguish transmitted symbols under actual channel conditions.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#interface-signal-eye)Micrometers of package wiring to board-scale links; schematic

Learning objectiveRelate digital error behavior to analog channel and timing margins.

## The mechanism

A digital link uses analog voltages or currents to encode symbols. Wires, connectors and package transitions attenuate and distort those signals; neighboring activity and supply noise add interference. A receiver needs enough voltage separation and timing margin to decide correctly. An eye diagram overlays many symbol intervals to reveal the available opening, while bit-error measurements test actual outcomes under stated conditions. Equalization can compensate for some channel loss but adds complexity and power. The IBM BoW interface study is a concrete example of signal and power analysis tied to a particular package implementation.

1.  Define the channel, symbol rate, receiver requirements and environmental conditions.
2.  Model or measure loss and reflections through each physical transition.
3.  Include aggressor activity, timing jitter and supply noise in the margin analysis.
4.  Inspect the received eye and measure errors with a documented test pattern and duration.
5.  Adjust routing, termination or equalization and repeat integrated testing over operating corners.

## Science and assumptions

### Unit interval

$$
\mathrm{UI}=\frac{1}{R_{\mathrm{symbol}}}
$$

Unit interval is the reciprocal of symbol rate.

A symbol can encode more than one bit; use symbol rate rather than payload bit rate here.

Symbols and units

UI

Symbol unit interval

s/symbol

R\_symbol

Symbol rate

symbols/s

Rsymbol is symbols/s and UI is seconds/symbol. Multi-level signaling may encode multiple bits per symbol.

Assumptions Symbol rate and bit rate must not be conflated; coding and overhead affect payload rate.

## Engineering example

Synthetic 10 Gsymbol/s link has a 100 ps unit interval. A 20 ps total timing uncertainty consumes one fifth of that interval before considering the receiver’s own requirements.

## Distinctions and tradeoffs

An ideal square-wave drawing is not a measured signal; zero errors in a short test does not prove a zero error probability.

Higher signaling rate or denser routing can raise bandwidth while reducing margin; equalization and extra spacing cost power or area.

Correct arithmetic is useless if package or network links corrupt data, retry excessively or fail under high simultaneous activity.

## Specifications and interfaces

Eye opening

Voltage and time margin

Volts and seconds at a stated measurement point.

Error rate

Errors / tested bits

Test duration and statistical confidence matter, especially with no observed errors.

### Interfaces

Transmitter and channel Input

Symbols distorted by channel loss, reflections and crosstalk

Receiver decision Output

Recovered symbols and observed error events

## Check your understanding

### Why can a link pass alone but fail beside busy neighbors?

1.  Bits change their mathematical definition
2.  Channel behavior never depends on activity
3.  Crosstalk or shared supply noise can reduce margin

Answer and reasoning

Crosstalk or shared supply noise can reduce margin

Neighboring transitions can disturb voltage or timing even though the intended logical data is unchanged.

## Evidence and scope

IBM’s numerical geometry results are not transferred to this example. Eye limits and test confidence must be specified for the actual interface.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [Signal and Power Integrity Design and Analysis for BoW Interface for Chiplet Integration on Advanced Packaging](https://research.ibm.com/publications/signal-and-power-integrity-design-and-analysis-for-bunch-of-wires-bow-interface-for-chiplet-integration-on-advanced-packaging)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/interface-signal-eye-d9fbfd204e435f5d.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)
-   [Clock tree and gated timing domains](https://semiaifoundry.com/learn/atlas/clock/)

### Related lessons

-   [Die-to-die links and UCIe compatibility](https://semiaifoundry.com/learn/atlas/die-link-compatibility/)
-   [Power integrity and transient voltage margin](https://semiaifoundry.com/learn/atlas/power-integrity-budget/)