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  "title": "On-chip metal and via hierarchy",
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  "description": "Connects cells through a multilayer electrical network.",
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  "revisionDate": "2026-10-07",
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  "topic": "Materials and wiring",
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      "url": "https://semiaifoundry.com/ai-atlas/#interconnect"
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    {
      "title": "IBM Research — Interconnect Performance and Scaling Strategy",
      "url": "https://research.ibm.com/publications/interconnect-performance-and-scaling-strategy-at-the-5-nm-node"
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      "title": "Insulators and low-k films",
      "url": "https://semiaifoundry.com/learn/atlas/dielectric/"
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  "content": "Materials and wiring · Atlas v1.3.0\n\n# On-chip metal and via hierarchy\n\nConnects cells through a multilayer electrical network.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#interconnect)Local nanometer features extending across millimeter-scale dies\n\nLearning objectiveUse a distributed RC approximation to explain why a longer unbuffered wire can have more than a proportional delay cost.\n\n## The mechanism\n\nA chip's metal stack turns individual circuits into a system. Short local lines connect nearby devices, while higher-level wiring can span larger regions; vias join selected levels. The layout is a routed network with physical resistance, capacitance, congestion, and reliability limits. Consequently, a logically short connection is not automatically fast or inexpensive. The atlas pulls the wiring layers apart while keeping their vertical vias connected, revealing how many paths cross without electrical contact. Each wire must terminate at the correct node, and its surroundings affect its signal. This hierarchy is one reason adding more arithmetic units does not guarantee proportional application speed: the units must exchange operands and results.\n\n1.  Route a cell’s output through a chosen conductive layer.\n2.  Use vias when a connection needs to move to another layer.\n3.  Deliver the signal to the correct destination while meeting resistance, capacitance, and routing constraints.\n\n## Science and assumptions\n\n### Distributed wire-delay scaling\n\n$$\nR=rL,\\qquad C=cL,\\qquad\\tau_{\\mathrm{wire}}\\propto rcL^2\n$$\n\nUniform-wire resistance and capacitance each scale with length. Their distributed-RC delay scales with resistance per length times capacitance per length times length squared.\n\nSymbols and units\n\nR\n\nWire resistance\n\nΩ\n\nC\n\nWire capacitance\n\nF\n\nr\n\nResistance per length\n\nΩ/m\n\nc\n\nCapacitance per length\n\nF/m\n\nL\n\nUnbuffered wire length\n\nm\n\nτ\\_wire\n\nCharacteristic RC wire delay\n\ns\n\nFor an unbuffered uniform wire, both resistance and capacitance grow with length, giving a quadratic length dependence in a simple RC model. This makes physical placement matter.\n\nAssumptions Distributed RC approximation with per-length r and c; driver resistance, repeaters, coupling, and inductance can change the actual delay law.\n\n## Engineering example\n\nSynthetic wire: r = 0.1 Ω/μm and c = 0.2 fF/μm over 100 μm give R = 10 Ω, C = 20 fF and RC = 200 fs. At 200 μm, R = 20 Ω and C = 40 fF, so RC = 800 fs. The product quadruples; the actual delay includes the model-dependent coefficient and driver.\n\n## Distinctions and tradeoffs\n\nCrossing lines in different metal layers are not connected unless the design provides the appropriate vertical connection.\n\nMore routing capacity uses area and layers. Narrower wiring may worsen resistance and signal delay.\n\nAI computation moves values between memory and arithmetic. Interconnect cost makes placement and data reuse essential.\n\n## Specifications and interfaces\n\nConnections\n\nLines + vias\n\nLateral routing and vertical level changes.\n\nDelay mechanism\n\nResistance and capacitance\n\nWire geometry and material influence both.\n\nScaling issue\n\nHigher narrow-wire resistance\n\nDocumented concern in advanced-node interconnect research.\n\n### Interfaces\n\nCell outputs Input\n\nSignal voltages and supply currents\n\nDestination cells Output\n\nRouted electrical connectivity\n\n## Check your understanding\n\n### Why can placing arithmetic near its operands help?\n\n1.  It can reduce data-movement distance and interconnect cost\n2.  It removes every arithmetic operation\n3.  It makes memory contents independent of power\n\nAnswer and reasoning\n\nIt can reduce data-movement distance and interconnect cost\n\nReal wires have delay and energy costs. Data locality reduces some of the movement surrounding useful arithmetic.\n\n## Evidence and scope\n\nThe linked interconnect work motivates resistance/capacitance scaling. Synthetic values illustrate an unbuffered uniform RC line, not a node-specific delay prediction; repeaters, coupling and inductance can change the result.\n\nUse the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.\n\n## Sources\n\n-   [IBM Research — Interconnect Performance and Scaling Strategy](https://research.ibm.com/publications/interconnect-performance-and-scaling-strategy-at-the-5-nm-node)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/interconnect-a5385c7d6ce18b1a.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Copper conductor and barrier](https://semiaifoundry.com/learn/atlas/copper-conductor/)\n-   [Insulators and low-k films](https://semiaifoundry.com/learn/atlas/dielectric/)\n\n### Related lessons\n\n-   [Device contact and interface resistance](https://semiaifoundry.com/learn/atlas/contact/)\n-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)\n-   [Six-transistor static memory cell](https://semiaifoundry.com/learn/atlas/sram/)\n-   [Clock tree and gated timing domains](https://semiaifoundry.com/learn/atlas/clock/)\n-   [On-chip interconnect fabric](https://semiaifoundry.com/learn/atlas/on-chip-network/)"
}