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      "title": "Explore in Atlas",
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      "title": "Intel: Announcing a New Era of Integrated Electronics",
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      "title": "NVIDIA GB200 NVL72 specifications",
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      "title": "Clock tree and gated timing domains",
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      "title": "Shared L2 cache",
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  "content": "Host platform · Atlas v1.3.0\n\n# Host CPU\n\nRuns the operating system and coordinates the workloads, data preparation, and I/O surrounding accelerated computation.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#host-cpu)Centimeter-scale packaged processor; functional blocks schematic\n\nLearning objectiveDistinguish serial fraction from accelerator speedup.\n\n## The mechanism\n\nThe CPU is the general-purpose processor that organizes the system’s work. It runs operating-system services, prepares tasks, launches GPU kernels, handles control-heavy code, and coordinates data and networking. GPUs accelerate many numerical operations, but a full AI service still needs request handling, tokenization, orchestration, memory management, and failure recovery. In a Grace Blackwell system, the CPU and GPUs have a coherent high-bandwidth connection; in other servers, the host path commonly uses PCIe. Neither arrangement makes software coordination free. The CPU can issue a workload, carry on with other work while the GPU executes, and react to the reported completion; coordination and data preparation still cost time. Separate control traffic from the much larger movement of tensor data so the division of labor becomes clear.\n\n1.  The CPU runs the software that receives requests, prepares data, and organizes the computation.\n2.  It dispatches suitable numerical work to GPUs while continuing other control and system tasks.\n3.  Completion events and results return to the software pipeline for subsequent processing, response delivery, or recovery.\n\n## Science and assumptions\n\n### The unaccelerated fraction limits total speedup\n\n$$\nS=\\frac{1}{(1-f)+f/s}\n$$\n\nOverall speedup is the reciprocal of the unaccelerated fraction plus the accelerated fraction divided by its speedup.\n\nSymbols and units\n\nS\n\nOverall fixed-workload speedup\n\ndimensionless\n\nf\n\nBaseline execution-time fraction accelerated\n\nfraction\n\ns\n\nSpeedup applied to that fraction\n\npositive dimensionless ratio\n\nf is the fraction of original execution time that a proposed accelerator can speed up, and s is its speedup for that portion. The remaining fraction includes tasks such as preparation, dispatch, serialization, or service logic. Even an arbitrarily fast GPU cannot eliminate time spent elsewhere. Measuring the complete application reveals which part deserves optimization next.\n\nAssumptions Amdahl’s fixed-workload model with unchanged serial work and no added transfer or coordination overhead. Real batching, overlap, and workload scaling can alter the fractions; a peak hardware throughput ratio is not automatically s.\n\n## Engineering example\n\nIf 10% of a workload is serial, infinite acceleration caps ideal speedup at 10× in Amdahl’s expression.\n\n## Distinctions and tradeoffs\n\nA fast GPU does not remove the need for general-purpose system software. CPU preparation, dispatch, and I/O coordination can still limit the overall service.\n\nA faster accelerator can expose CPU scheduling or preprocessing bottlenecks. Moving more work onto the GPU helps some pipelines while making others harder to coordinate.\n\nAn AI model becomes a usable service only when its numerical work is integrated with ordinary software tasks. The CPU supplies much of that general-purpose coordination.\n\n## Specifications and interfaces\n\nGrace core count\n\n72 Arm Neoverse V2 cores\n\nPer Grace CPU in the official GB200 configuration.\n\nGB200 pairing\n\n1 Grace CPU + 2 Blackwell GPUs\n\nPer Grace Blackwell Superchip.\n\nCPU–GPU interconnect\n\n900 GB/s raw bidirectional NVLink-C2C\n\nInterface rating; useful application bandwidth is workload dependent.\n\n### Interfaces\n\nUser/system work Input\n\nRequests, programs, and operating-system events\n\nAccelerator dispatch Output\n\nKernel launches, descriptors, and control\n\nHost memory Input\n\nProgram state and prepared data\n\n## Check your understanding\n\n### Which task naturally belongs to the CPU’s coordination role?\n\n1.  Serving as the liquid coolant.\n2.  Running the operating system and launching accelerator work.\n3.  Storing all HBM bits in one register.\n\nAnswer and reasoning\n\nRunning the operating system and launching accelerator work.\n\nThe CPU integrates accelerated numerical work into a functioning software system, including control-heavy and operating-system responsibilities.\n\n## Historical context\n\n### 1971 · Intel introduces the 4004 microprocessor\n\nIntel introduced the 4004 in November 1971. Integrating a programmable CPU on a chip made it practical to reuse a hardware design for different instruction sequences, advancing the general-purpose control layer that still coordinates modern accelerator systems.\n\n[Intel: Announcing a New Era of Integrated Electronics](https://www.intel.com/content/www/us/en/history/virtual-vault/articles/the-intel-4004.html)\n\n## Evidence and scope\n\nThe model excludes communication, memory and changing problem size.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [NVIDIA Data Center CPUs: Grace architecture](https://docs.nvidia.com/dccpu/index.html)\n-   [NVIDIA: Inside Grace CPU architecture](https://developer.nvidia.com/blog/inside-nvidia-grace-cpu-nvidia-amps-up-superchip-engineering-for-hpc-and-ai/)\n-   [NVIDIA GB200 NVL72 specifications](https://www.nvidia.com/en-us/data-center/gb200-nvl72/)\n-   [Intel Advisor: Amdahl’s Law and measurement](https://www.intel.com/content/www/us/en/docs/advisor/user-guide/2024-2/use-amdahl-law.html)\n-   [Intel: Announcing a New Era of Integrated Electronics](https://www.intel.com/content/www/us/en/history/virtual-vault/articles/the-intel-4004.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/host-cpu-31cd324b779e4ac6.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Clock tree and gated timing domains](https://semiaifoundry.com/learn/atlas/clock/)\n-   [Register file](https://semiaifoundry.com/learn/atlas/register-file/)\n-   [Shared L2 cache](https://semiaifoundry.com/learn/atlas/l2-cache/)\n\n### Related lessons\n\n-   [Grace Blackwell Superchip](https://semiaifoundry.com/learn/atlas/grace-blackwell-superchip/)\n-   [Grace LPDDR5X memory](https://semiaifoundry.com/learn/atlas/lpddr-memory/)\n-   [DDR5 server memory](https://semiaifoundry.com/learn/atlas/ddr-memory/)\n-   [PCI Express interconnect](https://semiaifoundry.com/learn/atlas/pcie-interface/)\n-   [Network interface adapter](https://semiaifoundry.com/learn/atlas/network-adapter/)"
}