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  "id": "atlas-lesson-hbm-tsv-reveal",
  "title": "TSV formation, keep-out and backside reveal",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Builds insulated vertical conductors and exposes their opposite ends for stacking.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Memory / HBM fabrication and assembly",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
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      "id": "section-1",
      "title": "TSV formation, keep-out and backside reveal",
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      "title": "Science and assumptions",
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      "title": "Via resistance and exclusion area",
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      "title": "Engineering example",
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      "title": "Distinctions and tradeoffs",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "Why does a TSV consume more layout area than its metal diameter suggests?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#hbm-tsv-reveal"
    },
    {
      "title": "DISCO — Tech Briefing 2023",
      "url": "https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf"
    },
    {
      "title": "SK hynix — Small Size, Big Impact",
      "url": "https://news.skhynix.com/en/small-size-big-impact/"
    },
    {
      "title": "Lam Research — Our Processes",
      "url": "https://www.lamresearch.com/products/our-processes/"
    },
    {
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    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "Through-silicon via",
      "url": "https://semiaifoundry.com/learn/atlas/through-silicon-via/"
    },
    {
      "title": "Plasma and wet etch: selectivity and profile",
      "url": "https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/"
    },
    {
      "title": "Temporary bonding, thinning and singulation",
      "url": "https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/"
    },
    {
      "title": "HBM stack assembly, repair and staged test",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/"
    },
    {
      "title": "HBM silicon intensity and allocation",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-silicon-intensity/"
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  "content": "Memory / HBM fabrication and assembly · Atlas v1.3.0\n\n# TSV formation, keep-out and backside reveal\n\nBuilds insulated vertical conductors and exposes their opposite ends for stacking.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#hbm-tsv-reveal)DRAM cell to vertical stack; routes and logical mapping are separate\n\nLearning objectiveDistinguish TSV fabrication, backside reveal and the area around a vertical connection.\n\n## The mechanism\n\nA through-silicon via carries a connection through a die rather than storing a DRAM bit. Its process needs a hole, electrical isolation from surrounding silicon, compatible conductor integration and access at both ends. The insertion point within wafer fabrication varies by route. Later thinning and backside processing reveal a buried connection and prepare it for joining. TSV stress, routing and electrical coupling can require space around the structure, affecting usable silicon area. The lesson follows one vertical path while keeping a TSV inside a die distinct from the bump or bond that connects that die to the next one.\n\n1.  Select and label where TSV insertion occurs relative to the memory-device process.\n2.  Etch the via structure and form the required insulating and conductor interfaces.\n3.  Fill and planarize the conductor while controlling voids and surrounding-material effects.\n4.  Support and thin the wafer to expose the opposite connection end in the chosen reveal route.\n5.  Prepare backside connections and test continuity/isolation before committing dies to a stack.\n\n## Science and assumptions\n\n### Via resistance and exclusion area\n\n$$\nR_{\\mathrm{via}}\\approx\\frac{\\rho L}{\\pi r^2},\\qquad A_{\\mathrm{exclusion}}\\approx\\pi(r+k)^2\n$$\n\nVia resistance is approximately resistivity times length divided by circular conductor area. The toy exclusion area uses a radius enlarged by the keep-out distance.\n\nSymbols and units\n\nR\\_via\n\nUniform via DC resistance\n\nΩ\n\nρ\n\nConductor resistivity\n\nΩ·m\n\nL\n\nConducting via length\n\nm\n\nr\n\nConducting via radius in the toy geometry\n\nm\n\nk\n\nRadial keep-out distance beyond that radius\n\nm\n\nA\\_exclusion\n\nCircular exclusion footprint\n\nm²\n\nρ in Ω·m, via length L/radius r and keep-out distance k in m give resistance Ω and area m².\n\nAssumptions Cylindrical uniform conductor and circular keep-out toy model. Contacts, liners, stress anisotropy and real layout change both results.\n\n## Engineering example\n\nSynthetic geometry: a 2 μm conductor radius with a 3 μm surrounding keep-out has a 5 μm exclusion radius, so its circular excluded area is 6.25 times the conductor area. This is not an HBM design rule.\n\n## Distinctions and tradeoffs\n\nA TSV and an inter-die bump are not the same physical connection, and TSV insertion order is not universal.\n\nSmaller or denser TSVs can reduce footprint while tightening etch/fill, isolation, stress and alignment requirements.\n\nVertical connections let stacked DRAM participate in a wide memory interface, while consuming area and manufacturing effort per delivered bit.\n\n## Specifications and interfaces\n\nPhysical path\n\nIn-die TSV plus inter-die joint\n\nDifferent structures with different process and failure mechanisms.\n\nArea demand\n\nVia, liner, keep-out and routing\n\nThe metal cross-section alone underestimates integration area.\n\n### Interfaces\n\nMemory wafer and via route Input\n\nDefined insertion stage, frontside structures and support\n\nBackside-accessible vertical connection Output\n\nRevealed conductor with compatible joining surface\n\n## Check your understanding\n\n### Why does a TSV consume more layout area than its metal diameter suggests?\n\n1.  Isolation, keep-out and routing space may also be needed\n2.  The entire silicon die becomes a via\n3.  Each TSV stores an extra DRAM bank\n\nAnswer and reasoning\n\nIsolation, keep-out and routing space may also be needed\n\nThe surrounding electrical and mechanical environment imposes area requirements beyond the conducting core.\n\n## Evidence and scope\n\nInsertion stage, materials, dimensions and keep-out rules are route-specific. The drawing does not establish a vendor’s via-first/middle/last flow.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [DISCO — Tech Briefing 2023](https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf)\n-   [SK hynix — Small Size, Big Impact](https://news.skhynix.com/en/small-size-big-impact/)\n-   [Lam Research — Our Processes](https://www.lamresearch.com/products/our-processes/)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/hbm-tsv-reveal-326c9d35c6e39dea.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Through-silicon via](https://semiaifoundry.com/learn/atlas/through-silicon-via/)\n-   [Plasma and wet etch: selectivity and profile](https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/)\n\n### Related lessons\n\n-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)\n-   [HBM stack assembly, repair and staged test](https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/)\n-   [HBM silicon intensity and allocation](https://semiaifoundry.com/learn/atlas/hbm-silicon-intensity/)"
}