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  "title": "HBM heat, assembly yield and test access",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Explain how added layers affect the heat path, screening strategy and delivered good stacks.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Memory",
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  "version": "1.3.0",
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      "id": "section-1",
      "title": "HBM heat, assembly yield and test access",
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      "title": "The mechanism",
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      "title": "Multiple heat sources",
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      "title": "Conditional assembly yield",
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      "title": "Specifications and interfaces",
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      "title": "Interfaces",
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      "title": "Check your understanding",
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      "title": "Why not multiply wafer yield into every already screened die again?",
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      "title": "Evidence and scope",
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      "title": "Sources",
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      "title": "Continue exploring",
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      "id": "section-15",
      "title": "Foundations",
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      "title": "Related lessons",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#hbm-stack-thermal-yield"
    },
    {
      "title": "imec — thermal STCO study of 3D HBM-on-GPU",
      "url": "https://www.imec-int.com/en/press/imec-mitigates-thermal-bottleneck-3d-hbm-gpu-architectures-using-system-technology-co"
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    {
      "title": "MIT OpenCourseWare — Introduction to Heat Transfer",
      "url": "https://ocw.mit.edu/courses/2-051-introduction-to-heat-transfer-fall-2015/"
    },
    {
      "title": "SK hynix — the team behind 12-layer HBM3",
      "url": "https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/"
    },
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      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "HBM layer count and physical height",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack-height-budget/"
    },
    {
      "title": "DFT, probe, binning and known-good die",
      "url": "https://semiaifoundry.com/learn/atlas/known-good-die-test/"
    },
    {
      "title": "Underfill, warpage, thermal paths and qualification",
      "url": "https://semiaifoundry.com/learn/atlas/package-thermomechanical-reliability/"
    },
    {
      "title": "Qualify the memory system and retain useful work",
      "url": "https://semiaifoundry.com/learn/atlas/memory-system-qualification/"
    },
    {
      "title": "HBM stack assembly, repair and staged test",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/"
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  "content": "Memory · Atlas v1.3.0\n\n# HBM heat, assembly yield and test access\n\nExplain how added layers affect the heat path, screening strategy and delivered good stacks.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#hbm-stack-thermal-yield)Thermal path and test population across a memory stack; schematic\n\nLearning objectiveExplain how added layers affect the heat path, screening strategy and delivered good stacks.\n\n## The mechanism\n\nEvery added die introduces heat sources, interfaces and opportunities for assembly damage. Heat follows several parallel paths through silicon, metal, polymer and the surrounding package; the hottest location is not necessarily the tallest die. Test coverage changes with access: a wafer test can inspect some die functions before stacking, while TSV chains, cross-die connections and the complete high-speed interface require later checks. A known-good input is a unit that passed a defined screen, not a physically perfect die. Assembly yield therefore starts from screened inputs and counts newly introduced failures, avoiding a second charge for the same wafer loss.\n\n1.  Define incoming wafer/die test coverage and preserve identity through thinning, singulation and stacking.\n2.  Measure continuity and functional behavior at the stages where test access exists; map errors to the same stack genealogy.\n3.  Estimate heat from each active layer using a stated power distribution and boundary temperature.\n4.  Inspect assembly defects with electrical tests plus suitable imaging; a hot spot or open circuit alone does not identify its cause.\n5.  Separate per-unit screening, product reliability qualification and observed in-service failure rates.\n\n## Science and assumptions\n\n### Multiple heat sources\n\n$$\nT_i-T_{\\mathrm{coolant}}=\\sum_j R_{ij}P_j\n$$\n\nTi − Tcoolant = Σj Rij Pj\n\nSymbols and units\n\nTi\n\nTemperature at inspected location i\n\n°C\n\nTcoolant\n\nSpecified coolant boundary temperature\n\n°C\n\nRij\n\nThermal coupling from source j to location i\n\nK/W\n\nPj\n\nHeat dissipated at source j\n\nW\n\nA thermal-resistance matrix represents how each heat source j contributes to temperature at location i, including cross-heating.\n\nAssumptions Linear steady-state approximation at specified boundaries. Transients and temperature-dependent properties require a richer model.\n\n### Conditional assembly yield\n\n$$\nY_{\\mathrm{assembly}}\\approx y_{\\mathrm{joint}}^{J}\n$$\n\nYassembly ≈ yjoint^J\n\nSymbols and units\n\nYassembly\n\nProbability a screened input set survives modeled assembly\n\nfraction\n\nyjoint\n\nConditional aggregate pass probability per interface\n\nfraction\n\nJ\n\nModeled interfaces\n\ncount\n\nJ is the number of independently modeled assembly interfaces, each with aggregate conditional pass probability yjoint.\n\nAssumptions Screened inputs; excludes residual input escapes, correlated defects, repair and common tooling failures. An interface probability is not a per-bump probability.\n\n## Engineering example\n\nSynthetic independent-interface model: 12 interfaces at 99.5% conditional pass probability yield about 94.2%; at 99.9%, about 98.8%. A shared contamination event violates independence. These values do not estimate any supplier’s yield.\n\n## Distinctions and tradeoffs\n\nTrack the denominator at each stage; conditional assembly loss acts on the units that actually enter assembly.\n\nEarlier screening avoids wasting downstream components, but adds handling, test time and cost; some failures are only observable after assembly.\n\nEffective stack supply and sustainable frequency depend on both manufacturability and thermal operation.\n\n## Specifications and interfaces\n\nYield denominator\n\nScreened input sets\n\nDo not multiply their original wafer yield a second time.\n\nThermal boundary\n\nLocation, power map and coolant\n\nStack-average temperature can hide local limits.\n\n### Interfaces\n\nDie screening Input\n\nCoverage, bin and residual escape risk\n\nStack test Output\n\nFunctional, interconnect and thermal evidence\n\n## Check your understanding\n\n### Why not multiply wafer yield into every already screened die again?\n\n1.  It double-counts losses already excluded from the incoming population\n2.  Screening guarantees zero future failures\n3.  HBM assembly cannot introduce faults\n\nAnswer and reasoning\n\nIt double-counts losses already excluded from the incoming population\n\nTrack the denominator at each stage; conditional assembly loss acts on the units that actually enter assembly.\n\n## Evidence and scope\n\nimec’s 2025 thermal study concerns a specified research HBM-on-GPU arrangement. It motivates spatial heat analysis; its simulated temperatures are not general product limits.\n\nAdjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.\n\n## Sources\n\n-   [imec — thermal STCO study of 3D HBM-on-GPU](https://www.imec-int.com/en/press/imec-mitigates-thermal-bottleneck-3d-hbm-gpu-architectures-using-system-technology-co)\n-   [MIT OpenCourseWare — Introduction to Heat Transfer](https://ocw.mit.edu/courses/2-051-introduction-to-heat-transfer-fall-2015/)\n-   [SK hynix — the team behind 12-layer HBM3](https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/hbm-stack-thermal-yield-0460105d4317f4c3.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [HBM layer count and physical height](https://semiaifoundry.com/learn/atlas/hbm-stack-height-budget/)\n-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)\n\n### Related lessons\n\n-   [Underfill, warpage, thermal paths and qualification](https://semiaifoundry.com/learn/atlas/package-thermomechanical-reliability/)\n-   [Qualify the memory system and retain useful work](https://semiaifoundry.com/learn/atlas/memory-system-qualification/)\n-   [HBM stack assembly, repair and staged test](https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/)"
}